Octal Transparent Latch
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54F 74F533 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F 74F533 Octal Transparent L...
Description
www.DataSheet4U.com
54F 74F533 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F 74F533 Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’F533 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state The ’F533 is the same as the ’F373 except that the outputs are inverted
Features
Y Y Y Y
Eight latches in a single package TRI-STATE outputs for bus interfacing Inverted version of the ’F373 Guaranteed 4000V minimum ESD protection
Commercial 74F533PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F533DM (Note 2) 74F533SC (Note 1) 74F533SJ (Note 1) 54F533FM (Note 2) 54F533LM (Note 2)
Note 1 Devices also available in 13
J20A M20B M20D W20A E20A
reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9548 – 3 TL F 9548–4 TL F 9548 – 2
TL F ...
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