MC10EP17 Datasheet: 3.3V / 5V ECL Quad Differential Driver/Receiver





MC10EP17 3.3V / 5V ECL Quad Differential Driver/Receiver Datasheet

Part Number MC10EP17
Description 3.3V / 5V ECL Quad Differential Driver/Receiver
Manufacture ON Semiconductor
Total Page 11 Pages
PDF Download Download MC10EP17 Datasheet PDF

Features: MC10EP17, MC100EP17 3.3 V / 5 V E CL Quad Differential Driver/Receiver D escription The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The > 3.0 GHz maximum fre quency provided by the high frequency o utputs makes the device ideal for buffe ring of very high speed oscillators. Th e VBB pin, an internally generated volt age supply, is available to this device only. For single-ended input condition s, the unused differential input is con nected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VC C via a 0.01ĂmF capacitor and limit cu rrent sourcing or sinking to 0.5 mA. Wh en not used, VBB should be left open. T he design incorporates two stages of ga in, internal to the device, making it a n excellent choice for use in high band width amplifier applications. Inputs of unused gates can be left open and will not affect the operation of the rest o f the device. All VCC and VEE pins must be externally connected.

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MC10EP17, MC100EP17
3.3 V / 5 V ECL Quad
Differential Driver/Receiver
Description
The MC10/100EP17 is a 4-bit differential line receiver based on the
EP17 device. The > 3.0 GHz maximum frequency provided by the
high frequency outputs makes the device ideal for buffering of very
high speed oscillators.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01ĂmF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
Features
220 ps Typical Propagation Delay
Maximum Frequency > 3.0 GHz Typical
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
http://onsemi.com
20
1
TSSOP20
DT SUFFIX
CASE 948E
SOIC20 WB
QFN20
DW SUFFIX
MN SUFFIX
CASE 751D05 CASE 485E01
MARKING DIAGRAMS*
20
MCXXX
EP17
ALYWG
G
1
20
MCXXXEP17
AWLYYWWG
1
20
1 XXXX
EP17
ALYWG
G
XXX
= 10 or 100
A = Assembly Location
L, = Assembly Lot
WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 Rev. 9
1
Publication Order Number:
MC10EP17/D

                    
           






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