Quad D Flip-Flop
MC74HC175A
Quad D Flip-Flop with Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC175A is identical ...
Description
MC74HC175A
Quad D Flip-Flop with Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of four D flip−flops with common Reset and Clock inputs, and separate D inputs. Reset (active−low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive going edge of the Clock input.
Features
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity 166 FETs or 41.5 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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16 1
MARKING DIAGRAMS
16
SOIC−16 D SUFFIX CASE 751B
HC175AG AWLYWW
1
16
16 1
TSSOP−16 DT SUFFIX CASE 948F
HC 175A ALYWG
G
1
A L, WL Y, YY W, WW G or G
= Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
(Note: Microdot may be in either location)
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