A/D Converter. ADC14V155 Datasheet
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with
The ADC14V155 is a high-performance CMOS analog-to-
digital converter with LVDS outputs. It is capable of converting
analog input signals into 14-Bit digital words at rates up to 155
Mega Samples Per Second (MSPS). Data leaves the chip in
a DDR (Dual Data rate) format; this allows both edges of the
output clock to be utilized while achieving a smaller package
size. This converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize power consumption and the external com-
ponent count, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
■ 1.1 GHz Full Power Bandwidth
■ Internal sample-and-hold circuit
■ Low power consumption
■ Internal precision 1.0V reference
■ Single-ended or Differential clock modes
■ Clock Duty Cycle Stabilizer
■ Dual +3.3V and +1.8V supply operation (+/- 10%)
■ Power-down and Sleep modes
■ Offset binary or 2's complement output data format
bandwidth of 1.1 GHz. The ADC14V155 operates from dual
+3.3V and +1.8V power supplies and consumes 951 mW of
power at 155 MSPS.
■ LVDS outputs
■ 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
The separate +1.8V supply for the digital output interface al- Key Specifications
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 15 mW while ■ Resolution
still allowing fast wake-up time to full operation. In addition ■ Conversion Rate
there is a sleep feature which consumes 50 mW of power and ■ SNR (fIN = 70 MHz)
has a faster wake-up time.
■ SFDR (fIN = 70 MHz)
swing equal to
provide a full
voltage. A stable
internal voltage reference is provided, or the ADC14V155 can ■ Power Consumption
be operated with an external reference.
71.7 dBFS (typ)
86.9 dBFS (typ)
11.5 bits (typ)
1.1 GHz (typ)
951 mW (typ)
Clock mode (differential versus single-ended) and output data
format (offset binary versus 2's complement) are pin-se-
lectable. A duty cycle stabilizer maintains performance over
a wide range of input clock duty cycles.
■ High IF Sampling Receivers
■ Wireless Base Station Receivers
It is available in a 48-lead LLP package and operates over the ■ Power Amplifier Linearization
industrial temperature range of −40°C to +85°C.
■ Multi-carrier, Multi-mode Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Radar Systems
© 2007 National Semiconductor Corporation 300052
Industrial (−40°C ≤ TA ≤ +85°C)
48 Pin LLP
Evaluation Board (0-150 MHz)
Evaluation Board (>150 MHz)
Pin Descriptions and Equivalent Circuits
Differential analog input pins. The differential full-scale input signal
level is two times the reference voltage with each input pin signal
centered on a common mode voltage, VCM.
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between VRP and VRN as close to the pins as possible,
and a 10 µF capacitor should be placed in parallel.
VRP and VRN should not be loaded. VRM may be loaded to 1mA for
use as a temperature stable 1.5V reference.
It is recommended to use VRM to provide the common mode
voltage, VCM, for the differential analog inputs, VIN+ and VIN−.
This pin can be used as either the +1.0V internal reference voltage
output (internal reference operation) or as the external reference
voltage input (external reference operation).
To use the internal reference, VREF should be decoupled to AGND
with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In
wwwt.DhaitsaSmheeot4dUe.co,mVREF defaults as the output for the internal 1.0V
To use an external reference, overdrive this pin with a low noise
external reference voltage. The input impedance looking into this
pin is 9kΩ. Therefore, to overdrive this pin, the output impedance
of the external reference source should be << 9kΩ.
This pin should not be used to source or sink current.
The full scale differential input voltage range is 2 * VREF.
This is a four-state pin controlling the input clock mode and output
CLK_SEL/DF = VA, CLK+ and CLK− are configured as a
differential clock input. The output data format is 2's complement.
CLK_SEL/DF = (2/3)*VA, CLK+ and CLK− are configured as a
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1/3)*VA, CLK+ is configured as a single-ended
clock input and CLK− should be tied to AGND. The output data
format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock
input and CLK− should be tied to AGND. The output data format is
This is a three-state input controlling Power Down and Sleep
PD = VA, Power Down is enabled. In the Power Down state only
the reference voltage circuitry remains active and power dissipation
PD = VA/2, Sleep mode is enabled. Sleep mode is similar to Power
Down mode - it consumes more power but has a faster recovery
PD = AGND, Normal operation.