Document
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture
– 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny261/461/861) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861) Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny261/461/861) – Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features – 8/16-bit Timer/Counter with Prescaler and Two PWM Channels – 8/10-bit High Speed Timer/Counter with Separate Prescaler 3 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time Generator – Universal Serial Interface with Start Condition Detector – 10-bit ADC 11 Single Ended Channels 16 Differential ADC Channel Pairs 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x) www.DataSheet4U.com – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator I/O and Packages – 16 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC and 32-pad MLF Operating Voltage: – 1.8 - 5.5V for ATtiny261V/461V/861V – 2.7 - 5.5V for ATtiny261/461/861 Speed Grade: – ATtiny261V/461V/861V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny261/461/861: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption – Active Mode: 1 MHz, 1.8V: 380μA – Power-down Mode: 0.1μA at 1.8V
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8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny261/V ATtiny461/V ATtiny861/V Preliminary
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2588B–AVR–11/06
1. Pin Configurations
Figure 1-1. Pinout ATtiny261/461/861
PDIP/SOIC
(MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (OC1B/PCINT11) PB3 VCC GND (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1) PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND AVCC PA4 (ADC3/ICP0/PCINT4) PA5 (ADC4/AIN2/PCINT5) PA6 (ADC5/AIN0/PCINT6) PA7 (ADC6/AIN1/PCINT7)
32 31 30 29 28 27 26 25
PB2 (SCK/USCK/SCL/OC1B/PCINT10) PB1 (MISO/DO/OC1A/PCINT9) PB0 (MOSI/DI/SDA/OC1A/PCINT8) NC NC NC PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1)
NC (OC1B/PCINT11) PB3 NC VCC GND NC (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
1 2 3 4 5 6 7 8
QFN/MLF
24 23 22 21 20 19 18 17
NC PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND NC NC AVCC PA4 (ADC3/ICP0/PCINT4)
Note:
The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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ATtiny261/461/861
2588B–AVR–11/06
NC (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 NC (ADC6/AIN1/PCINT7) PA7 (ADC5/AIN0/PCINT6) PA6 (ADC4/AIN2/PCINT5) PA5 NC
9 10 11 12 13 14 15 16
ATtiny261/461/861
2. Overview
The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
GND VCC
Watchdog Timer Watchdog Oscillator
Power Supervision POR / BOD & RESET
debugWIRE
PROGRAM LOGIC
Oscillator Circuits / Clock Generation
Flash
SRAM
CPU EEPROM
AVCC AGND AREF
Timer/Counter0
DATABUS
Timer/Counter1
A/D Conv.
USI
Analog Comp.
Internal Bandgap
3
11
PORT B (8)
PORT A (8)
RESET XTAL[1..2] PB[0..7] PA[0..7]
3
2588B–AVR–11/06
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM.