Serial EEPROM. AT34C02B Datasheet

AT34C02B EEPROM. Datasheet pdf. Equivalent

AT34C02B Datasheet
Recommendation AT34C02B Datasheet
Part AT34C02B
Description Two-wire Serial EEPROM
Feature AT34C02B; Features • Permanent and Reversible Software Write Protection for the First-half of the Array – Soft.
Manufacture ATMEL Corporation
Datasheet
Download AT34C02B Datasheet




ATMEL Corporation AT34C02B
Features
Permanent and Reversible Software Write Protection for the First-half of the Array
– Software Procedure to Verify Write Protect Status
Hardware Write Protection for the Entire Array
Low-voltage and Standard-voltage Operation
– 1.7 (VCC = 1.7V to 3.6V)
Internally Organized 256 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.7V) and 400 kHz (2.7V and 3.6V) Compatibility
16-byte Page Write Modes
Partial Page Writes Are Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball
dBGA2 Packages
Description
The AT34C02B provides 2048 bits of serial electrically-erasable and programmable
read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of
the device incorporates a permanent and a reversible software write protection feature
while hardware write protection for the entire array is available via an external pin.
Once the permanent software write protection is enabled, by sending a special com-
mand to the device, it cannot be reversed. However, the reversible software write
protection is enabled and can be reversed by sending awwws.DpaetaSchieaet4lUc.coommmand. The hard-
ware write protection is controlled with the WP pin and can be used to protect the
entire array, whether or not the software write protection has been enabled. This
allows the user to protect none, first-half, or all of the array depending on the applica-
tion. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operations are essential. The AT34C02B is avail-
able in space saving 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead
TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface.
It is available in 1.7V (1.7V to 3.6V).
Table 1. Pin Configurations
Pin Name Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL Serial Clock Input
WP Write Protect
8-lead TSSOP
8-ball dBGA2
8-lead Ultra Thin Mini-MAP
VCC
WP
SCL
SDA
8
7
6
5
1 A0
2 A1
3 A2
4 GND
VCC
WP
SCL
SDA
8
7
6
5
1 A0
2 A1
3 A2
4 GND
Bottom View
(MLP 2x3)
Bottom View
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Two-wire Serial
EEPROM
with Permanent
and Reversible
Software Write
Protect
2K (256 x 8)
AT34C02B
Note: Not recommended for new
design; please refer to
AT34C02C datasheet.
Rev. 3417E–SEEPR–1/07
1



ATMEL Corporation AT34C02B
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125 °C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1. Block Diagram
VCC
GND
WP
SCL
SDA
A2
A1
A0
START
STOP
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
R/W
SERIAL
CONTROL
LOGIC
EN
WRITE PROTECT
CIRCUITRY
COMP
LOAD INC
DATA WORD
ADDR/COUNTER
H.V. PUMP/TIMING
DATA RECOVERY
SOFTWARE WRITE
PROTECTED AREA
(00H - 7FH)
EEPROM
Y DEC
SERIAL MUX
DIN
DOUT
DOUT/ACK
LOGIC
2 AT34C02B
3417E–SEEPR–1/07



ATMEL Corporation AT34C02B
AT34C02B
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device
address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other
AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be
addressed on a single bus system. (Device addressing is discussed in detail under
“Device Addressing,” page 9.) A device is selected when a corresponding hardware and
software match is true. If these pins are left floating, the A2, A1, and A0 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear
during customer applications, Atmel recommends always connecting the address pins
to a known state. When using a pull-up resistor, Atmel recommends using 10kor less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected directly to Vcc, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND. However, due to capacitive coupling that may appear during customer applica-
tions, Atmel recommends always connecting the WP pins to a known state. When using
a pull-up resistor, Atmel recommends using 10kor less.
Table 2. AT34C02B Write Protection Modes
WP Pin Status
Permanent Write Protect
Register
VCC
GND or Floating
Not Programmed
GND or Floating
Programmed
GND or Floating
Reversible Write Protect
Register
Not Programmed
Programmed
Part of the Array Write
Protected
Full Array (2K)
Normal Read/Write
First-Half of Array
(1K: 00H - 7FH)
First-Half of Array
(1K: 00H - 7FH)
Table 3. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 100 kHz, VCC = +1.7V
Symbol Test Condition
Max
CI/O
CIN
Note:
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
1. This parameter is characterized and is not 100% tested.
8
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
3417E–SEEPR–1/07
3







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