NLSF1174

NLSF1174 Hex D Flip−Flop with Common Clock and Reset This device consists of six D flip−flops with common Clock and Reset inputs. Each flip−flop is loaded with a low−to−high transition of the Clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible. Features http://onsemi.com Output Drive Compatibility: 10 LSTTL Loads Outputs Directly Interface to CMOS Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA MSL Level 1 Chip Complexity: 162 FET Pb−Free Package is Available* 1 QFN−16 MN SUFFIX CASE 485G MARKING DIAGRAM Q0 16 Reset 15 VCC 14 Q5 13 ÇÇÇ ÇÇÇ 16 1 12 www.DataSheet4U.com D5 NLSF1174 A L Y W G NLSF 1174 ALYW G G D0 1 D1 2 11 D4 = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Q1 3 10 Q4 (Note: Microdot may be in either location) D2 4 9 D3 Reset FUNCTION TABLE Inputs Clock X D X H L L X X Output Q L H L No Change No Change 5 Q2 6 GND 7 Clock 8 Q3 L H H H H Center pad on bottom may be connected to VCC of device. This pad must be isolated or connected to VCC. Figure 1. PIN ASSIGNMENT (Top View) ORDERING INFORMATION Device NLSF1174MNR2 NLSF1174MNR2G Package QFN−16 Shipping† 3000 / Tape & Reel QFN−16 3000 / Tape & Reel (Pb−Free) *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, ...