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SY100EP451L Dataheets PDF



Part Number SY100EP451L
Manufacturers Micrel Semiconductor
Logo Micrel Semiconductor
Description 3.3V ECL 6-Bit Differential Register
Datasheet SY100EP451L DatasheetSY100EP451L Datasheet (PDF)

SY10/100EP451L 3.3V ECL 6-Bit Differential Register with Master Reset General Description The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have an internal 75k Ω pull-down resistor. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are.

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SY10/100EP451L 3.3V ECL 6-Bit Differential Register with Master Reset General Description The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have an internal 75k Ω pull-down resistor. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE +1.2V, the clamp will override and force the output to a default state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Features • • • • • • • • • 450ps typical propagation delay Maximum frequency > 3.0GHz typical Asynchronous Master Reset 20ps skew within device, 35ps skew device-to-device PECL mode operating range: – VCC = 3.0V to 3.6V with VEE = 0V NECL mode operating range: – VCC = 0V with VEE = –3.0V to –3.6V Open input default state Safety clamp on inputs Available in 32-pin TQFP Applications • High Speed Logic • Wireless Communication Systems • Data Communication Systems www.DataSheet4U.com Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com March 2007 M9999-030507-A [email protected] or (408) 955-1690 Micrel, Inc. SY10/100EP451L Logic Diagram March 2007 2 M9999-030507-A [email protected] or (408) 955-1690 Micrel, Inc. SY10/100EP451L Ordering Information(1) Part Number SY10EP451LTG SY10EP451LTGTR SY100EP451LTG SY100EP451LTGTR Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. (2) (2) Package Type T32-1 T32-1 T32-1 T32-1 Operating Range Industrial Industrial Industrial Industrial Package Marking SY10EP451LTG with Pb-Free bar-line indicator SY10EP451LTG with Pb-Free bar-line indicator SY100EP451LTG with Pb-Free bar-line indicator SY100EP451LTG with Pb-Free bar-line indicator Lead Finish Pb-Free NiPdAu Pb-Free NiPdAu Pb-Free NiPdAu Pb-Free NiPdAu Pin Configuration 32-Pin TQFP (T32-1) March 2007 3 M9999-030507-A [email protected] or (408) 955-1690 Micrel, Inc. SY10/100EP451L Pin Description Pin Number 2, 3 32, 1 30, 31 26, 27 24, 25 22, 23 29 4, 5 Pin Name D0, /D0 D1, /D1 D2, /D2 D3, /D3 D4, /D4 D5, /D5 MR CLK, /CLK ECL Master Reset Input pin. If input pin is left open, it will default to LOW. ECL Differential Clock Input: This input pair is the clock signal input to the device. Each input pin is connected to a 75kΩ pull-down resistor. Due to an internal clamping circuit, CLK will default LOW and /CLK will default HIGH if left open. ECL Differential Data Inputs: These input pairs are the different data signal inputs to the device. Each input pin is connected to a 75kΩ pull-down resistor. Due to an internal clamping circuit, D will default LOW and /D will default HIGH if left open. Pin Function 7, 8 9, 10 11, 12 14, 15 17, 18 20, 21 6, 13, 16 19, 28 Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 VCC VEE ECL Differential Data Outputs: Q defaults to LOW and /Q defaults to HIGH if D inputs are left open. See “LVPECL Output Interface Applications” section for recommendations on terminations. Positive Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to the VCC pins as possible. Negative Power Supply: VEE must be tied to most negative supply. March 2007 4 M9999-030507-A [email protected] or (408) 955-1690 Micrel, Inc. SY10/100EP451L Absolute Maximum Ratings(1) Supply Voltage PECL Mode (VCC) ............................................................... +4V NECL Mode (VEE) ............................................................... –4V Input Voltage (VIN) PECL Mode ..........................................................................VCC NECL Mode ......................................................................... VEE Output Current (IOUT) Continuous........................................................................ 50mA Surge............................................................................... 100mA Lead Temperature (soldering, 20sec.) ....................................260°C Storage Temperature (Ts)...................................... –65°C to +150°C Operating Ratings(2) Supply Voltage (VCC) PECL Mode (VEE =0V)…………………. +3.0V to +3.6V Supply Voltage (VEE) NECL Mode (VCC =0V)…………………. -3.0V to -3.6V Ambient Temperature (TA)....................................... –40°C to +85°C (3) Junction Thermal Resistance TQFP Junction-to-Ambient (θJA) 0lfpm......................................................................... 80°C/W 500lfpm .................................................................... 66°C/W Junction-to-Case (θJC) ..................................................


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