SY89841U
Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer
General Description
The SY89841U is a low jitter LVDS, 2:1 input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89841U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or “runt” pulses during switchover. In addition, a unique Fail-safe Input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV).
Precision Edge®
Features
• Selects between two sources, and provides a glitch-free, stable LVDS output • Guaranteed AC performance over temperature and supply voltage: – wide operating frequency: 1kHz to >1.5GHz – <870ps In-to-Out tpd – <150ps tr/tf The differential input includes Micrel’s unique, 3-pin • Unique patent-pending input isolation design input termination architecture that allows customers minimizes crosstalk to interface to any differential signal (AC- or DC• Fail-safe input prevents oscillations coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the • Ultra-low jitter design: signal path. The outputs are 350mV, LVDS with fast – <1psrms random jitter rise/fall times guaranteed to be less than 150ps. – <1psrms cycle-to-cycle jitter – <10pspp total jitter (clock) The SY89841U operates from a 2.5V ±5% supply www.DataSheet4U.com – <0.7psrms MUX crosstalk induced jitter and is guaranteed over the full industrial temperature range of –40°C to +85°C. The • Unique patent-pending input termination and VT SY89841U is part of Micrel’s high-speed, Precision pin accepts DC-coupled and AC-coupled inputs Edge® product line. All support documentation can (CML, PECL, LVDS) be found on Micrel’s web site at: www.micrel.com. • 350mV LVDS output swing • 2.5V +5% power supply • –40°C to +85°C industrial temperature range • Available in 16-pin (3mm x 3mm) MLF™ package
Applications
• Redundant clock switchover • Fail-safe clock protection
Markets
• • • • LAN/WAN Enterprise servers ATE Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
February 2005
M9999-021405
[email protected] or (408) 955-1690
Micrel, Inc.
SY89841U
Typical Application
Primary Clock From System IN0 50Ω VT0 50Ω /IN0 VREF-AC0 IN1 50Ω VT1 50Ω /IN1 VREF-AC1 SEL (LVTTL/CMOS)
2:1 MUX 0
Primary Clock Secondary Clock
MUX
SEL
Select Primary
Select Secondary
1
S
OUTPUT Runt pulse eliminated from output Switchover occurs
Secondary Clock From Local Oscillator
Runt Pulse Elimination Logic
Simplified Example Illustrating Runt Pulse Eliminator (RPE) Circuit when Primary Clock Fails
February 2005
2
M9999-021405
[email protected] or (408) 955-1690
Micrel, Inc.
SY89841U
Ordering Information(1)
Part Number Package Type MLF-16 MLF-16 Operating Range Industrial Industrial Package Marking Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
SY89841UMG SY89841UMGTR(2)
Notes:
841U with Pb-Free bar-line Indicator 841U with Pb-Free bar-line Indicator
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only. 2. Tape and Reel.
Pin Configuration
VREF-AC1
14
VT1
16 /IN0 VREF-AC0 VT0 IN0 1 2 3 4 5
15
/IN1
13 12 11 10 9 VCC CAP SEL GND 8
IN1
6
7
VCC
Q
16-Pin MLF™ (MLF-16)
February 2005
3
VCC
/Q
M9999-021405
[email protected] or (408) 955-1690
Micrel, Inc.
SY89841U
Pin Description
Pin Number 4, 1, 16, 13 Pin Name IN0, /IN0, IN1, /IN1 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Please refer to the “Input Interface Applications” section for more details. Reference Voltage: This output biases to VCC –1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. See the “Input Interface Applications” section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See the “Input Interface Applications” section for more details. Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins as possible. Differential Outputs: This LVDS differential output is a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table below for details. This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logi.