Document
SCAN18540T Inverting Line Driver with 3-STATE Outputs
October 1991 Revised May 2000
SCAN18540T Inverting Line Driver with 3-STATE Outputs
General Description
The SCAN18540T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).
Features
s IEEE 1149.1 (JTAG) compliant s Dual output enable signals per byte s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP (Shrink Small Outline Package) s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN products
Ordering Code:
Order Number SCAN18540TSSC Package Number MS54A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Connection Diagram
Pin Descriptions
Pin Names AI(0–8) BI(0–8) AOE1, AOE2 BOE1, BOE2 AO(0–8) BO(0–8) Description Input pins, A side Input pins, B side 3-STATE Output Enable Input pins, A side 3-STATE Output Enable Input pins, B side Output pins, A side Output pins, B side
Truth Tables
Inputs AOE1 L H X L AOE2 L X H L Inputs BOE1 L H X L BOE2 L X H L BI(0–8) H X X L BO(0–8) L Z Z H AI(0–8) H X X L AO(0–8) L Z Z H
H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance
© 2000 Fairchild Semiconductor Corporation
DS010964
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SCAN18540T
Block Diagrams
Byte-A
Tap Controller
Byte-B
Note: BSR stands for Boundary Scan Register
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SCAN18540T
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 MSB→LSB Instruction Code 00000000 10000001 10000010 The INSTRUCTION register is an 8-bit register which captures the default value of 01001101. The two least significant bits of this captured value (01) are required by IEEE 00000011 All Others Instruction EXTEST SAM.