Alterable EEPROM. X28C512 Datasheet

X28C512 Datasheet PDF, Equivalent


Part Number

X28C512

Description

(X28C512 / X28C513) Byte Alterable EEPROM

Manufacture

Intersil Corporation

Total Page 21 Pages
PDF Download
Download X28C512 Datasheet PDF


X28C512 Datasheet
®
Data Sheet
X28C512, X28C513
June 7, 2006
FN8106.2
5V, Byte Alterable EEPROM
The X28C512, X28C513 are 64K x 8 EEPROM, fabricated
with Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile
memories, the X28C512, X28C513 are 5V only devices. The
X28C512, X28C513 feature the JEDEC approved pin out for
byte wide memories, compatible with industry standard
EPROMS.
The X28C512, X28C513 support a 128-byte page write
operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512, X28C513 also feature DATA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512, X28C513 support the software data
protection option.
www.DataSheet4U.com
Features
• Access Time: 90ns
• Simple Byte and Page Write
- Single 5V supply
• No external high voltages or VPP control circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low Power CMOS
- Active: 50mA
- Standby: 500µA
• Software Data Protection
- Protects data against system level inadvertent writes
• High Speed Page Write Capability
• Highly Reliable Direct WriteCell
- Endurance: 100,000 write cycles
- Data retention: 100 years
- Early end of write detection
- DATA polling
- Toggle bit polling
• Two PLCC and LCC Pinouts
- X28C512
• X28C010 EPROM pin compatible
- X28C513
• Compatible with lower density EEPROMs
• Pb-Free Plus Anneal Available (RoHS Compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X28C512 Datasheet
Block Diagram
A7-A15
X28C512, X28C513
X Buffers
Latches and
Decoder
512Kbit
EEPROM
Array
A0-A6
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
Ordering Information
PART NUMBER
X28C512D
X28C512DM
X28C512J
X28C513EM
X28C512D-12
X28C512DI-12
X28C512DMB-12
X28C512FMB-12
X28C512J-12*
X28C512JZ-12* (See Note)
X28C512JI-12
X28C512JIZ-12* (See Note)
X28C512JM-12
X28C512KM-12
X28C512PI-12
X28C512RMB-12
X28C513EM-12
X28C513EMB-12
X28C513J-12*
X28C513JZ-12* (Note)
X28C513JI-12*
X28C513JIZ-12* (Note)
X28C513JM-12
CE
OE
WE
VCC
VSS
Control
Logic and
Timing
I/O0-I/O7
Data Inputs/Outputs
PART MARKING
X28C512D
X28C512DM
X28C512J
X28C513EM
X28C512D-12
X28C512DI-12
X28C512DMB-12
X28C512FMB-12
X28C512J-12
X28C512J-12 Z
X28C512JI-12
X28C512JI-12 Z
X28C512JM-12
X28C512KM-12
X28C512PI-12
X28C512RMB-12
X28C513EM-12
X28C513EMB-12
X28C513J-12
X28C513J-12 Z
X28C513JI-12
X28C513JI-12 Z
X28C513JM-12
ACCESS TIME
(ns)
-
120
TEMP RANGE (°C)
0 to +70
-55 to +125
0 to +70
-55 to +125
0 to +70
-40 to +85
Mil-STD-883
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
-55 to +125
-40 to +85
Mil-STD-883
-55 to +125
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
PACKAGE
32 Ld CERDIP
32 Ld CERDIP
32 Ld PLCC
32 Ld LCC
32 Ld CERDIP
32 Ld CERDIP
32 Ld CERDIP
32 Ld Flat Pack
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
36 Ld CPGA
32 Ld PDIP
32 Ld Flat Pack
32 Ld LCC
32 Ld LCC
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
2 FN8106.2
June 7, 2006


Features Datasheet pdf ® X28C512, X28C513 Data Sheet June 7, 2006 FN8106.2 5V, Byte Alterable EEPRO M The X28C512, X28C513 are 64K x 8 EEPR OM, fabricated with Intersil’s propri etary, high performance, floating gate CMOS technology. Like all Intersil prog rammable nonvolatile memories, the X28C 512, X28C513 are 5V only devices. The X 28C512, X28C513 feature the JEDEC appro ved pin out for byte wide memories, com patible with industry standard EPROMS. The X28C512, X28C513 support a 128-byte page write operation, effectively prov iding a 39µs/byte write cycle and enab ling the entire memory to be written in less than 2.5 seconds. The X28C512, X2 8C513 also feature DATA Polling and Tog gle Bit Polling, system software suppor t schemes used to indicate the early co mpletion of a write cycle. In addition, the X28C512, X28C513 support the softw are data protection option. Features Access Time: 90ns • Simple Byte an d Page Write - Single 5V supply • No external high voltages or VPP control circuits - Self-timed • No erase be.
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