X28HC256 EEPROM Datasheet

X28HC256 Datasheet, PDF, Equivalent


Part Number

X28HC256

Description

Byte Alterable EEPROM

Manufacture

Intersil Corporation

Total Page 19 Pages
Datasheet
Download X28HC256 Datasheet


X28HC256
DATASHEET
256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM
X28HC256
The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing a
highly reliable 5V only nonvolatile memory.
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling the
entire memory to be typically rewritten in less than 0.8s. The
X28HC256 also features DATA polling and Toggle bit polling,
two methods of providing early end of write detection. The
X28HC256 also supports the JEDEC standard software data
protection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data retention
of 100 years.
Features
• Access time: 90ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VP-P control circuits
- Self timed
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- Active: 60mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Writecell
- Endurance: 100,000 cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• RoHS compliant
August 27, 2015
FN8108.5
A0 TO A14
ADDRESS
INPUTS
CE
OE
WE
VCC
VSS
X BUFFERS
LATCHES AND
DECODER
256k BIT
EEPROM
ARRAY
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
I/O BUFFERS
AND LATCHES
I/O0 TO I/O7
DATA INPUTS/OUTPUTS
FIGURE 1. BLOCK DIAGRAM
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2007, 2010, 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

X28HC256
X28HC256
Ordering Information
PART NUMBER
(Note 4)
PART MARKING
ACCESS TIME
(ns)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
X28HC256JZ-15 (Notes 1, 3) X28HC256J-15 ZHY
150
0 to +70
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC256JI-15 (Note 1)
X28HC256JI-15 HY
150
-40 to +85 32 Ld PLCC
N32.45x55
X28HC256JIZ-15
(Notes 1, 3)
X28HC256JI-15 ZHY
150
-40 to +85 32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC256PZ-15
(Notes 2, 3)
X28HC256P-15 HYZ
150
0 to +70
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256PIZ-15
(Notes 2, 3)
X28HC256PI-15 HYZ
150
-40 to +85 28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256JZ-12 (Notes 1, 3) X28HC256J-12 ZHY
120
0 to +70
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC256JI-12 (Note 1)
X28HC256JI-12 HY
120
-40 to +85 32 Ld PLCC
N32.45x55
X28HC256JIZ-12
(Notes 1, 3)
X28HC256JI-12 ZHY
120
-40 to +85 32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC256PZ-12
(Notes 2, 3)
X28HC256P-12 HYZ
120
0 to +70
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256PIZ-12
(Notes 2, 3)
X28HC256PI-12 HYZ
120
-40 to +85 28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256SZ-12 (Note 3)
X28HC256S-12 HYZ
120
0 to +70
28 Ld SOIC (300mils RoHS Compliant) MDP0027
X28HC256SI-12
X28HC256SI-12 HY
120
-40 to +85 28 Ld SOIC (300mils)
M28.3
X28HC256SIZ-12 (Note 3) X28HC256SI-12 HYZ
120
-40 to +85 28 Ld SOIC (300mils RoHS Compliant) MDP0027
X28HC256JZ-90 (Notes 1, 3) X28HC256J-90 ZHY
90
0 to +70
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC256JI-90 (Note 1)
X28HC256JI-90 HY
90
-40 to +85 32 Ld PLCC
N32.45x55
X28HC256JIZ-90
(Notes 1, 3)
X28HC256JI-90 ZHY
90
-40 to +85 32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC256PZ-90
(Notes 2, 3)
X28HC256P-90 HYZ
90
0 to +70
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256PIZ-90 (Notes 2, 3) X28HC256PI-90 HYZ
90
-40 to +85 28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256SI-90
X28HC256SI-90 HY
90
-40 to +85 28 Ld SOIC (300mils)
M28.3
X28HC256SIZ-90 (Note 3) X28HC256SI-90 HYZ
90
-40 to +85 28 Ld SOIC (300mils RoHS Compliant) MDP0027
NOTES:
1. Add “T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for X28HC256. For more information on MSL, please see tech brief TB363.
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2
FN8108.5
August 27, 2015


Features DATASHEET 256k, 32k x 8-Bit, 5V, Byte A lterable EEPROM X28HC256 The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providi ng a highly reliable 5V only nonvolatil e memory. The X28HC256 supports a 128-b yte page write operation, effectively p roviding a 24µs/byte write cycle, and enabling the entire memory to be typica lly rewritten in less than 0.8s. The X2 8HC256 also features DATA polling and T oggle bit polling, two methods of provi ding early end of write detection. The X28HC256 also supports the JEDEC standa rd software data protection feature for protecting against inadvertent writes during power-up and power-down. Enduran ce for the X28HC256 is specified as a m inimum 100,000 write cycles per byte an d an inherent data retention of 100 yea rs. Features • Access time: 90ns • Simple byte and page write - Single 5V supply - No external high voltages or VP-P control circuits - Self ti.
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