X40430 Monitor Datasheet

X40430 Datasheet, PDF, Equivalent


Part Number

X40430

Description

(X40430 - X40435) Triple Voltage Monitor

Manufacture

Intersil Corporation

Total Page 24 Pages
Datasheet
Download X40430 Datasheet


X40430
X40430, X40431, X40434, X40435
® 4Kbit EEPROM
Data Sheet
July 29, 2005
FN8251.0
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Monitoring voltages: 5V to 9V
• Independent core voltage monitor
• Triple voltage detection and reset assertion
—Standard reset threshold settings. See selec-
tion table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three separate voltages
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• Memory security
www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
manual reset, and Block Lockprotect serial EEPROM
in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersil’s unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X40430
BLOCK DIAGRAM
X40430, X40431, X40434, X40435
V3MON
V2MON
V3 Monitor
Logic
+
-
V2 Monitor
Logic
VTRIP3
VCC or
V2MON*
+
VTRIP2
-
SDA
Data
Register
WP Command
Decode Test
& Control
SCL Logic
Fault Detection
Register
Status
Register
EEPROM
Array
VCC
(V1MON)
*X40430, X40431=V2MON
X40434, X40435 =VCC
VCC Monitor
Logic
+
VTRIP1
-
Watchdog
and
Reset Logic
Power-on,
Manual Reset
Low Voltage
Reset
Generation
V3FAIL
V2FAIL
WDO
MR
RESET
X40430/34
RESET
X40431/35
LOWLINE
Device
Expected System
Voltages
Vtrip1(V)
X40430, X40431
-A 5V; 3V or 3.3V; 1.8V
-B 5V; 3V; 1.8V
-C 3.3V; 2.5V; 1.8V
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.95–3.05*
X40434, X40435
-A 5V; 3.3V; 1.5V
-B 5V; 3V or 3.3V; 1.5V
-C 5V; 3 or 3.3V; 1.2V
2.0–4.75*
4.55–4.65*
4.55–4.65*
4.55–4.65*
*Voltage monitor requires Vcc to operate. Others are independent of Vcc.
Vtrip2(V)
1.70–4.75
2.85–2.95
2.55–2.65
2.15–2.25
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
Vtrip3(V)
1.70–4.75
1.65–1.75
1.65–1.75
1.65–1.75
1.70–4.75
3.05–3.15
2.85–2.95
2.85–2.95
POR
(system)
RESET = X40430
RESET = X40431
RESET = X40434
RESET = X40435
PIN CONFIGURATION
X40430, X40434
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
X40431, X40435
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes
HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to VSS or VCC when not used. The
V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435).
3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when
VCC > VTRIP1.
4 NC No connect.
2 FN8251.0
July 29, 2005


Features ® X40430, X40431, X40434, X40435 4Kbit EEPROM FN8251.0 Data Sheet July 29, 20 05 Triple Voltage Monitor with Integra ted CPU Supervisor FEATURES • Monitor ing voltages: 5V to 9V • Independent core voltage monitor • Triple voltage detection and reset assertion —Stand ard reset threshold settings. See selec tion table on page 2. —Adjust low vol tage reset threshold voltages using spe cial programming sequence —Reset sign al valid to VCC = 1V —Monitor three s eparate voltages • Fault detection re gister • Selectable power-on reset ti meout (0.05s, 0.2s, 0.4s, 0.8s) • Sel ectable watchdog timer interval (25ms, 200ms, 1.4s or off) • Debounced manua l reset input • Low power CMOS —25 A typical standby current, watchdog on —6µA typical standby current, watch dog off • Memory security www.DataShe et4U.com • 4Kbits of EEPROM —16 byt e page write mode —5ms write cycle ti me (typical) • Built-in inadvertent w rite protection —Power-up/power-down protection circuitry —Block lock protect 0, or 1/2, of EEPROM • 400.
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