X40430 Monitor Datasheet

X40430 Datasheet, PDF, Equivalent


Part Number

X40430

Description

(X40430 / X40431) Triple Voltage Monitor

Manufacture

Xicor

Total Page 24 Pages
Datasheet
Download X40430 Datasheet


X40430
Preliminary Information
4kbit EEPROM
X40430/X40431
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
www.DataSheet4U.com — 5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I2C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lockprotect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
V3MON
V2MON
V3 Monitor
Logic
+
VTRIP3
-
V2 Monitor
Logic
+
VTRIP2
-
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
REV 1.2.3 11/28/00
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLoMgoicnitor
+
VTRIP1
-
www.xicor.com
Watchdog
and
Reset Logic
WDO
MR
Power on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40430
RESET
X40431
LOWLINE
Characteristics subject to change without notice. 1 of 24

X40430
X40430/X40431 – Preliminary Information
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I2C bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
X40430
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
X40431
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC
when not used.
3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high
when VCC > VTRIP1.
4 NC No connect.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the tPURST thereafter.
6 RESET/ RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever
RESET
VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power up. It will also stay active until manual reset is released
and for tPURST thereafter.
RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever
VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power up. It will also stay active until manual reset is released
and for tPURST thereafter.
7 VSS Ground
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 2 of 24


Features Preliminary Information 4kbit EEPROM X4 0430/X40431 DESCRIPTION The X40430/31 c ombines power-on reset control, watchdo g timer, supply voltage supervision, se condary and third voltage supervision, manual reset, and Block Lock™ protect serial EEPROM in one package. This com bination lowers system cost, reduces bo ard space requirements, and increases r eliability. Applying voltage to VCC act ivates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply a nd system oscillator to stabilize befor e the processor can execute code. Low V CC detection circuitry protects the use r’s system from low voltage condition s, resetting the system when VCC falls below the minimum VTRIP1 point. RESET/ RESET is active until VCC returns to pr oper operating level and stabilizes. A second and third voltage monitor circui t tracks the unregulated supply to prov ide a power fail warning or monitors di fferent power supply voltage. Three common low voltage combinations.
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