DatasheetsPDF.com

X40430 Dataheets PDF



Part Number X40430
Manufacturers Xicor
Logo Xicor
Description (X40430 / X40431) Triple Voltage Monitor
Datasheet X40430 DatasheetX40430 Datasheet (PDF)

Preliminary Information 4kbit EEPROM X40430/X40431 DESCRIPTION The X40430/31 combines power-on reset control, watchdog timer, supply voltage supervision, secondary and third voltage supervision, manual reset, and Block Lock™ protect serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power su.

  X40430   X40430



Document
Preliminary Information 4kbit EEPROM X40430/X40431 DESCRIPTION The X40430/31 combines power-on reset control, watchdog timer, supply voltage supervision, secondary and third voltage supervision, manual reset, and Block Lock™ protect serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VTRIP1 point. RESET/ RESET is active until VCC returns to proper operating level and stabilizes. A second and third voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Xicor’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. Triple Voltage Monitor with Integrated CPU Supervisor FEATURES • Triple voltage detection and reset assertion —Three standard reset threshold settings (4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V, 2.9V/1.7V/2.4V) —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to VCC = 1V —Monitor three voltages or detect power fail • Fault detection register • Selectable power on reset timeout • Selectable watchdog timer interval • Debounced manual reset input • Low power CMOS —30µA typical standby current, watchdog on —10µA typical standby current, watchdog off • 4Kbits of EEPROM —16 byte page write mode —Self-timed write cycle —5ms write cycle time (typical) www.DataSheet4U.com • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block lock protect 0, 1/4, 1/2, all of EEPROM • 400kHz I2C interface • 2.4V to 5.5V power supply operation • Available packages —14-lead SOIC, TSSOP BLOCK DIAGRAM V3MON V3 Monitor Logic V2MON + VTRIP3 + VTRIP2 - V3FAIL V2 Monitor Logic V2FAIL SDA WP Data Register Command Decode Test & Control Logic Fault Detection Register Status Register EEPROM Array Watchdog and Reset Logic WDO MR SCL VCC (V1MON) VCC Monitor Logic + VTRIP1 - Power on, Manual Reset Low Voltage Reset Generation RESET X40430 RESET X40431 LOWLINE REV 1.2.3 11/28/00 www.xicor.com Characteristics subject to change without notice. 1 of 24 X40430/X40431 – Preliminary Information A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. PIN CONFIGURATION X40430 14-Pin SOIC, TSSOP V2FAIL V2MON LOWLINE NC MR RESET VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC WDO V3FAIL V3MON WP SCL SDA V2FAIL V2MON LOWLINE NC MR RESET VSS X40431 14-Pin SOIC, TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC WDO V3FAIL V3MON WP SCL SDA The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock protection. The array is internally organized as x 8. The device features a 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN DESCRIPTION Pin 1 2 Name V2FAIL V2MON Function V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin. V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. No connect. Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter. RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below .


X40434 X40430 X40431


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)