X4285 Supervisor Datasheet

X4285 Datasheet, PDF, Equivalent


Part Number

X4285

Description

(X4283 / X4285) CPU Supervisor

Manufacture

Xicor

Total Page 22 Pages
Datasheet
Download X4285 Datasheet


X4285
Preliminary Information
128K
X4283/85
16K x 8 Bit
CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
www.DataSheet4U.com
Block Lockprotection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead TSSOP
DESCRIPTION
The X4283/85 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the set minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Four industry
BLOCK DIAGRAM
WP
SDA
SCL
S0
S1
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
VCC
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4283)
RESET (X4285)
REV 1.17 11/27/00
www.xicor.com
Characteristics subject to change without notice. 1 of 22

X4285
X4283/85 – Preliminary Information
standard Vtrip thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software proto-
col allowing operation on an 2-wire bus.
PIN CONFIGURATION
8-Pin JEDEC SOIC
S0
S1
RST/RST
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin TSSOP
WP
VCC
S0
S1
1
2
3
4
8 SCL
7 SDA
6 VSS
5 RST/RST
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
46
57
68
71
82
Name
S0
S1
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense level for 250ms. RESET/
RESET goes active if the Watchdog Timer is enabled and SDA remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling edge
on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes
active on power up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
REV 1.17 11/27/00
www.xicor.com
Characteristics subject to change without notice. 2 of 22


Features Preliminary Information 128K X4283/85 C PU Supervisor with 128K EEPROM DESCRIPT ION 16K x 8 Bit FEATURES • Selectab le watchdog timer • Low VCC detection and reset assertion —Four standard r eset threshold voltages —Adjust low V CC reset threshold voltage using specia l programming sequence —Reset signal valid to VCC = 1V • Low power CMOS <20µA max standby current, watchdog o n —<1µA standby current, watchdog OF F —3mA active current • 128Kbits of EEPROM —64 byte page write mode —S elf-timed write cycle —5ms write cycl e time (typical) • Built-in inadverte nt write protection —Power-up/power-d own protection circuitry —Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 by tes of EEPROM array with programmable B lock Lock™ protection www.DataSheet4U .com • 400kHz 2-wire interface • 2. 7V to 5.5V power supply operation • A vailable packages —8-lead SOIC —8-l ead TSSOP BLOCK DIAGRAM Watchdog Transi tion Detector WP Data Register Command Decode & Control Logic VCC Threshold Reset logic Block Lock Control Pr.
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