CPU Supervisor. X4283 Datasheet

X4283 Datasheet PDF, Equivalent


Part Number

X4283

Description

(X4283 / X4285) CPU Supervisor

Manufacture

Intersil Corporation

Total Page 22 Pages
PDF Download
Download X4283 Datasheet


X4283 Datasheet
®
Data Sheet
May 23, 2006
X4283, X4285
128K, 16K x 8 Bit
FN8121.1
CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
www.DataSheet4U.com 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
The X4283, X4285 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the set minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Four industry
standard Vtrip thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SDA
SCL
S0
S1
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET (X4283)
RESET (X4285)
Power-on and
VCC
VTRIP
+
-
Low Voltage
Reset
Generation
Kb=Kilobyte
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X4283 Datasheet
X4283, X4285
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software
protocol allowing operation on an 2-wire bus.
PIN CONFIGURATION
8-Pin JEDEC SOIC
S0
S1
RST/RST
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin TSSOP
WP
VCC
S0
S1
1
2
3
4
8 SCL
7 SDA
6 VSS
5 RST/RST
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
46
57
68
71
82
Name
S0
S1
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain ac-
tive until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up
and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
2 FN8121.1
May 23, 2006


Features Datasheet pdf ® X4283, X4285 128K, 16K x 8 Bit Data Sheet May 23, 2006 FN8121.1 CPU Superv isor with 128K EEPROM FEATURES • Sele ctable watchdog timer • Low VCC detec tion and reset assertion —Four standa rd reset threshold voltages —Adjust l ow VCC reset threshold voltage using sp ecial programming sequence —Reset sig nal valid to VCC = 1V • Low power CMO S —<20µA max standby current, watchd og on —<1µA standby current, watchdo g OFF —3mA active current • 128Kbit s of EEPROM —64 byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • Built-in inadv ertent write protection —Power-up/pow er-down protection circuitry —Protect 0, 1/4, 1/2, all or 64, 128, 256 or 51 2 bytes of EEPROM array with programmab le Block Lock™ protection • 400kHz 2-wire interface www.DataSheet4U.com 2.7V to 5.5V power supply operation Available packages —8 Ld SOIC —8 Ld TSSOP • Pb-free plus anneal avail able (RoHS compliant) BLOCK DIAGRAM Watchdog Transition Detector WP SDA Data Register Command Decode & Control L.
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