X4323 Supervisor Datasheet

X4323 Datasheet, PDF, Equivalent


Part Number

X4323

Description

(X4323 / X4325) CPU Supervisor

Manufacture

Intersil Corporation

Total Page 22 Pages
Datasheet
Download X4323 Datasheet


X4323
®
Data Sheet
X4323, X4325
32k, 4k x 8 Bit
May 25, 2006
FN8122.1
CPU Supervisor with 32k EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog off
—3mA active current
• 32Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
— 8 Ld SOICwww.DataSheet4U.com
—8 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
The X4323, X4325 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Serial EEPROM Memory in one
package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the RESET/RESET
signal. The user selects the interval from three preset
values. Once selected, the interval does not change,
even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Four industry
standard VTRIP thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SDA
SCL
S0
S1
VCC
Watchdog Transition
Detector
Protect Logic
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Status
Register
EEPROM Array
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4323)
RESET (X4325)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X4323
PIN CONFIGURATION
X4323, X4325
8-Pin JEDEC SOIC
S0
S1
RST/RST
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin TSSOP
WP
VCC
S0
S1
1
2
3
4
8 SCL
7 SDA
6 VSS
5 RST/RST
PIN FUNCTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
46
57
68
71
82
Name
S0
S1
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain ac-
tive until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up-
power-up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the de-
vice. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
2 FN8122.1
May 25, 2006


Features ® X4323, X4325 32k, 4k x 8 Bit Data Sh eet May 25, 2006 FN8122.1 CPU Supervis or with 32k EEPROM FEATURES • Selecta ble watchdog timer • Low VCC detectio n and reset assertion —Four standard reset threshold voltages —Adjust low VCC reset threshold voltage using speci al programming sequence —Reset signal valid to VCC = 1V • Low power CMOS <20µA max standby current, watchdog on —<1µA standby current, watchdog o ff —3mA active current • 32Kbits of EEPROM —64-byte page write mode —S elf-timed write cycle —5ms write cycl e time (typical) • Built-in inadverte nt write protection —Power-up/power-d own protection circuitry —Block Lock (1, 2, 4, 8 pages, all, none) • 400kH z 2-wire interface • 2.7V to 5.5V pow er supply operation • Available packa ges www.DataSheet4U.com —8 Ld SOIC 8 Ld TSSOP • Pb-free plus anneal ava ilable (RoHS compliant) DESCRIPTION Th e X4323, X4325 combines four popular fu nctions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one p.
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