CPU Supervisor. X5001 Datasheet

X5001 Datasheet PDF, Equivalent


Part Number

X5001

Description

CPU Supervisor

Manufacture

Xicor

Total Page 19 Pages
PDF Download
Download X5001 Datasheet PDF


X5001 Datasheet
X5001
CPU Supervisor
Features
• 200ms Power On Reset Delay
• Low Vcc Detection and Reset Assertion
—Five Standard Reset Threshold Voltages
—Adjust Low Vcc Reset Threshold Voltage using
special programming sequence
—Reset Signal Valid to Vcc=1V
• Selectable Nonvolatile Watchdog Timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current, Watchdog On
—<1µA Max Standby Current, Watchdog Off
• 2.7V to 5.5V Operation
• SPI Mode 0 interface
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Watchdog Change Latch
• High Reliability
www.DataSheet4U.com Available Packages
—8-Lead TSSOP
—8-Lead SOIC
—8 Pin PDIP
Block Diagram
DESCRIPTION
This device combines three popular functions, Power on
Reset, Watchdog Timer, and Supply Voltage Supervision
in one package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET signal after a
selectable time-out interval. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET is asserted until Vcc returns to proper
operating levels and stabilizes. Five industry standard
VTRIP thresholds are available, however, Xicor’s unique
circuits allow the thresold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
The device utilizes Xicor’s proprietary Direct WriteTM cell
for the Watchdog TImer control bits and the VTRIP stor-
age element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
SI
SO
SCK
CS/WDI
VCC
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
WATCHDOG
TRANSITION
DETECTOR
VTRIP
+
-
©Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
7078 1.1 8/9/99 CM
1
WATCHDOG
TIMER
RESET &
WATCHDOG
TIMEBASE
POWER ON/
LOW VOLTAGE
RESET
GENERATION
RESET
Characteristics subject to change without notice
7036 FRM 01

X5001 Datasheet
X5001
PIN DESCRIPTION
PIN PIN
(SOIC/PDIP) TSSOP
Name
1 1 CS/WDI
2 2 SO
5 8 SI
6 9 SCK
3 6 VPE
4 7 VSS
8 14 VCC
7 13 RESET
3-5,10-12
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog
bits present on the SI pin. The falling edge of SCK changes the data output on
the SO pin.
VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last
valid programmed level. To readjust the VTRIP level, requires that the VPE pin
be pulled to a high voltage (15-18V).
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active
whenever Vcc falls below the minimum Vcc sense level. It will remain active un-
til Vcc rises above the minimum Vcc sense level for 200ms. RESET goes active
if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW
longer than the selectable Watchdog time-out period. A falling edge of CS/WDI
will reset the Watchdog Timer. RESET goes active on power up at 1V and re-
mains active for 200ms after the power supply stabilizes.
No internal connections
Figure 1. PIN CONFIGURATION
RESET
VCC
CS/WDI
SO
8 Lead TSSOP
18
27
36
45
SCK
SI
V SS
VPE
8 Lead SOIC/PDIP
CS/WDI
SO
VPE
VSS
1
2
3
4
8 VCC
7 RESET
6 SCK
5 SI
2


Features Datasheet pdf X5001 CPU Supervisor Features • 200ms Power On Reset Delay • Low Vcc Detect ion and Reset Assertion —Five Standar d Reset Threshold Voltages —Adjust Lo w Vcc Reset Threshold Voltage using spe cial programming sequence —Reset Sign al Valid to Vcc=1V • Selectable Nonvo latile Watchdog Timer —0.2, 0.6, 1.4 seconds —Off selection —Select sett ings through software • Long Battery Life With Low Power Consumption —<50 A Max Standby Current, Watchdog On — <1µA Max Standby Current, Watchdog Off • 2.7V to 5.5V Operation • SPI Mod e 0 interface • Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Watchdog Chang e Latch • High Reliability www.DataSh eet4U.com • Available Packages —8-L ead TSSOP —8-Lead SOIC —8 Pin PDIP DESCRIPTION This device combines three popular functions, Power on Reset, Watc hdog Timer, and Supply Voltage Supervis ion in one package. This combination lo wers system cost, reduces board space requirements, and increases reliability. The Watchdog Timer provides an.
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