CPU Supervisor. X5001 Datasheet

X5001 Datasheet PDF, Equivalent


Part Number

X5001

Description

CPU Supervisor

Manufacture

Intersil Corporation

Total Page 20 Pages
PDF Download
Download X5001 Datasheet


X5001 Datasheet
®
Data Sheet
CPU Supervisor
FEATURES
• 200ms power-on reset delay
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Selectable nonvolatile watchdog timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
• 2.7V to 5.5V operation
• SPI mode 0 interface
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Watchdog change latch
• High reliability
• Available packages
— 8 Ld TSSOPwww.DataSheet4U.com
—8 Ld SOIC
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
Watchdog
Transition
Detector
VCC
VTRIP
+
-
May 30, 2006
X5001
FN8125.1
DESCRIPTION
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low VCC detection circuitry. When
VCC falls below the minimum VCC trip point, the system
is reset. RESET is asserted until VCC returns to proper
operating levels and stabilizes. Five industry standard
VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The device utilizes Intersil’s proprietary Direct Write
cell for the watchdog timer control bits and the VTRIP
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
Watchdog
Timer
Reset &
Watchdog
Timebase
Power-on/
Low Voltage
REset
Generation
RESET
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X5001 Datasheet
X5001
Ordering Information
PART NUMBER PART MARKING VCC RANGE (V)
X5001P-2.7
X5001P F
2.7 to 5.5
X5001PZ-2.7 (Note) X5001P ZF
VTRIP RANGE
2.55 to 2.7
X5001PI-2.7
X5001P G
X5001PIZ-2.7 (Note) X5001P ZG
X5001S8-2.7
X5001S8Z-2.7
(Note)
X5001S8I-2.7
X5001S8IZ-2.7
(Note)
X5001V8-2.7
X5001V8Z-2.7
(Note)
X5001V8I-2.7
X5001V8IZ-2.7
(Note)
X5001P-2.7A
X5001PZ-2.7A
(Note)
X5001PI-2.7A
X5001PIZ-2.7A
(Note)
X5001S8-2.7A
X5001S8Z-2.7A
(Note)
X5001S8I-2.7A
X5001S8IZ-2.7A
(Note)
X5001V8-2.7A
X5001V8Z-2.7A
(Note)
X5001V8I-2.7A
X5001V8IZ-2.7A
(Note)
X5001PI
X5001PIZ (Note)
X5001 F
X5001 ZF
X5001 G
X5001 ZG
501 F
5001 FZ
501 G
5001 GZ
X5001P AN
X5001P ZAN
X5001P AP
X5001P ZAP
X5001 AN
X5001 ZAN
X5001 AP
X5001 ZAP
501 AN
5001 ANZ
501 AP
5001 APZ
X5001P I
X5001P ZI
2.85 to 3.0
4.5 to 5.5
4.25 to 4.5
X5001S8
X5001S8Z (Note)
X5001
X5001 Z
X5001S8I
X5001S8IZ (Note)
X5001 I
X5001 ZI
TEMP. RANGE
(°C)
PACKAGE
0 to 70
8 Ld PDIP
0 to 70
8 Ld PDIP (300 mil)
(Pb-free)
-40 to 85
8 Ld PDIP
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
0 to 70
8 Ld SOIC (150 mil)
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
-40 to 85
8 Ld SOIC (150 mil)
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
0 to 70
8 Ld TSSOP (4.4mm)
0 to 70
8 Ld TSSOP (4.4mm)
(Pb-free)
-40 to 85 8 Ld TSSOP (4.4mm)
-40 to 85
8 Ld TSSOP (4.4mm)
(Pb-free)
0 to 70
8 Ld PDIP
0 to 70
8 Ld PDIP (300 mil)
(Pb-free)
-40 to 85
8 Ld PDIP
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
0 to 70
8 Ld SOIC (150 mil)
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
-40 to 85
8 Ld SOIC (150 mil)
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
0 to 70
8 Ld TSSOP (4.4mm)
0 to 70
8 Ld TSSOP (4.4mm)
(Pb-free)
-40 to 85 8 Ld TSSOP (4.4mm)
-40 to 85
8 Ld TSSOP (4.4mm)
(Pb-free)
-40 to 85
8 Ld PDIP
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
0 to 70
8 Ld SOIC (150 mil)
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
-40 to 85
8 Ld SOIC (150 mil)
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
2
PKG. DWG. #
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
FN8125.1
May 30, 2006


Features Datasheet pdf ® X5001 Data Sheet May 30, 2006 FN8125 .1 CPU Supervisor FEATURES • 200ms p ower-on reset delay • Low VCC detecti on and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using spec ial programming sequence —Reset signa l valid to VCC = 1V • Selectable nonv olatile watchdog timer —0.2, 0.6, 1.4 seconds —Off selection —Select set tings through software • Long battery life with low power consumption —<50 µA max standby current, watchdog on <1µA max standby current, watchdog of f • 2.7V to 5.5V operation • SPI mo de 0 interface • Built-in inadvertent write protection —Power-up/power-dow n protection circuitry —Watchdog chan ge latch • High reliability • Avail able packages www.DataSheet4U.com —8 Ld TSSOP —8 Ld SOIC —8 Ld PDIP • Pb-free plus anneal available (RoHS com pliant) BLOCK DIAGRAM Watchdog Transiti on Detector SI SO SCK CS/WDI Data Regis ter Command Decode & Control Logic DESCRIPTION This device combines three popular functions, Poweron Reset, Wat.
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