LVDS Buffer. DS25BR100 Datasheet

DS25BR100 Buffer. Datasheet pdf. Equivalent

DS25BR100 Datasheet
Recommendation DS25BR100 Datasheet
Part DS25BR100
Description 3.125 Gbps LVDS Buffer
Feature DS25BR100; DS25BR100 3.125 Gbps LVDS Buffer with PE and EQ April 2007 DS25BR100 3.125 Gbps LVDS Buffer with T.
Manufacture National Semiconductor
Datasheet
Download DS25BR100 Datasheet





National Semiconductor DS25BR100
April 2007
DS25BR100
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
General Description
The DS25BR100 is a single channel 3.125 Gbps LVDS buffer
optimized for high-speed signal transmission over lossy FR-4
printed circuit board backplanes and balanced metallic ca-
bles. Fully differential signal paths ensure exceptional signal
integrity and noise immunity.
The DS25BR100 features transmit pre-emphasis (PE) and
receive equalization (EQ), making it ideal for use as a re-
peater device. Other LVDS devices with similar IO character-
istics include the following products. The DS25BR120
features four levels of pre-emphasis for use as an optimized
driver device, while the DS25BR110 features four levels of
equalization for use as an optimized receiver device. The
DS25BR150 is a buffer/repeater with the lowest power con-
sumption and does not feature transmit pre-emphasis nor
receive equalization.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires minimal
space on the board while the flow-through pinout allows easy
board layout. The differential inputs and outputs are internally
terminated with a 100resistor to lower device input and out-
put return losses, reduce component count, and further min-
imize board space.
Features
DC - 3.125 Gbps low jitter, high noise immunity, low power
operation
Receive equalization reduces ISI jitter due to media loss
Transmit pre-emphasis drives lossy backplanes and
cables
On-chip 100input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
7 kV ESD on LVDS I/O pins protects adjoining
components
Small 3 mm x 3 mm 8-LLP space saving package
Applications
Clock and data buffering
Metallic cable driving and equalization
FR-4 equalization
Typical Application
© 2007 National Semiconductor Corporation 201791
20179110
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National Semiconductor DS25BR100
Block Diagram
Pin Diagram
20179101
20179104
Pin Descriptions
Pin Name
EQ
IN+
IN-
PE
NC
OUT-
OUT+
VCC
GND
Pin Name
1
2
3
4
5
6
7
8
DAP
Pin Type
Input
Input
Input
Input
NA
Output
Output
Power
Power
Pin Description
Equalizer select pin.
Non-inverting LVDS input pin.
Inverting LVDS input pin.
Pre-emphasis select pin.
"NO CONNECT" pin.
Inverting LVDS output pin.
Non-inverting LVDS Output pin.
Power supply pin.
Ground pad (DAP - die attach pad).
Control Pins (PE and EQ) Truth Table
EQ PE
Equalization Level
0 0 Low (Approx. 4 dB at 1.56 GHz)
0 1 Low (Approx. 4 dB at 1.56 GHz)
1 0 Medium (Approx. 8 dB at 1.56 GHz)
1 1 Medium (Approx. 8 dB at 1.56 GHz)
Pre-emphasis Level
Off
Medium (Approx. 6 dB at 1.56 GHz)
Off
Medium (Approx. 6 dB at 1.56 GHz)
Ordering Codes and Configurations
NSID
Function
DS25BR100TSD
DS25BR110TSD
DS25BR120TSD
DS25BR150TSD
Buffer/Repeater
Receiver
Driver
Buffer/Repeater
Available Equalization
Levels
Low / Medium
Off / Low / Medium / High
NA
NA
Available Pre-emphasis
Levels
Off / Medium
NA
Off / Low / Medium / High
NA
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2



National Semiconductor DS25BR100
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
LVCMOS Input Voltage (EQ, PE)
LVDS Input Voltage (IN+, IN−)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
LVDS Differential Input Voltage ((IN+) - (IN−))
0V to 1V
LVDS Output Voltage (OUT+, OUT−)
−0.3V to +4V
LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V
LVDS Output Short Circuit Current
Duration
5 ms
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SDA Package
2.08W
Derate SDA Package
16.7 mW/°C above +25°C
Package Thermal Resistance
 θJA
 θJC
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
+60.0°C/W
+12.3°C/W
7 kV
250V
1250V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Min Typ Max
Supply Voltage (VCC)
3.0 3.3 3.6
Receiver Differential Input
1.0
Voltage (VID)
Operating Free Air
−40 +25 +85
Temperature (TA)
Units
V
V
°C
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
LVCMOS INPUT DC SPECIFICATIONS (EQ, PE)
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIH High Level Input Current
IIL Low Level Input Current
VCL Input Clamp Voltage
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VIN = 3.6V
VCC = 3.6V
VIN = GND
VCC = 3.6V
ICL = −18 mA, VCC = 0V
2.0
GND
VOD
ΔVOD
Differential Output Voltage
Change in Magnitude of VOD for Complimentary
Output States
RL = 100Ω
250
-35
VOS
ΔVOS
Offset Voltage
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
1.05
-35
IOS Output Short Circuit Current (Note 8)
COUT
ROUT
Output Capacitance
Output Termination Resistor
OUT to GND, PE = 0
OUT to VCC, PE = 0
Any LVDS Output Pin to GND
Between OUT+ and OUT-
Typ
0
0
-0.9
350
1.2
-35
7
1.2
100
Max
VCC
0.8
±10
±10
−1.5
450
35
1.375
35
-55
55
Units
V
V
μA
μA
V
mV
mV
V
mV
mA
mA
pF
Ω
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