X9221A Potentiometer Datasheet

X9221A Datasheet, PDF, Equivalent


Part Number

X9221A

Description

Dual Digitally Controlled Potentiometer

Manufacture

Intersil Corporation

Total Page 15 Pages
Datasheet
Download X9221A Datasheet


X9221A
®
Data Sheet
X9221A
64 Taps, 2-Wire Serial Bus
August 30, 2006
FN8163.2
Dual Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Two XDCPs in one package
• 2-wire serial interface
• Register oriented format, 8 registers total
—Directly write wiper position
—Read wiper position
—Store as many as four positions per pot
• Instruction format
—Quick transfer of register contents to resistor
array
• Direct write cell
—Endurance–100,000 writes per bit per register
• Resistor array values
—2kΩ, 10kΩ, 50kΩ
• Resolution: 64 taps each pot
• 20 Ld plastic DIP and 20 Ld SOIC packages
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9221A integrates two digitally controlled potenti-
ometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non-
volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
www.DataSheet4U.com
VCC
VSS
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
8
Data
Pot 0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Register
Array
Pot 1
VH1/RH1
VL1/RL1
VW1/RW1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X9221A
X9221A
Ordering Information
PART NUMBER
X9221AYS
X9221AYSZ (Note)
X9221AYSI*
X9221AYSIZ* (Note)
X9221AWS*
PART MARKING
X9221AYS
X9221AYS Z
X9221AYSI
X9221AYSI Z
X9221AWS
VCC LIMITS
(V)
5 ±10%
RTOTAL (k)
2
TEMP
RANGE (°C)
PACKAGE
0 to +70 20 Ld SOIC (300MIL)
0 to +70 20 Ld SOIC (300MIL) (Pb-Free)
-40 to +85 20 Ld SOIC (300MIL)
-40 to +85 20 Ld SOIC (300MIL) (Pb-Free)
10 0 to +70 20 Ld SOIC (300MIL)
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
X9221AWSZ* (Note) X9221AWS Z
X9221AWSI*
X9221AWSI
X9221AWSIZ* (Note) X9221AWSI Z
X9221AUP
X9221AUP
X9221AUPZ (Note) X9221AUPZ
X9221AUPI
X9221AUPI
X9221AUPIZ (Note) X9221AUPIZ
X9221AUSI*
X9221AUSI
X9221AUSIZ* (Note) X9221AUSI Z
0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
-40 to +85 20 Ld SOIC (300MIL)
MDP0027
-40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
50 0 to +70 20 Ld PDIP
MDP0031
0 to +70 20 Ld PDIP (Pb-Free)
MDP0031
-40 to +85 20 Ld PDIP
MDP0031
-40 to +85 20 Ld PDIP (Pb-Free)
MDP0031
-40 to +85 20 Ld SOIC (300MIL)
MDP0027
-40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Potentiometer Pins
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9221A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
Address
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A
VH/RH(VH0/RH0-VH1/RH1), VL/RL (VL0/RL0-VL1/RL1)
The VH/RH and VL/RL inputs are equivalent to the ter-
minal connections on either end of a mechanical
potentiometer.
VW/RW (VW0/RW0-VW1/RW1)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
PIN CONFIGURATION
VW0/RW0
VL0/RL0
VH0/RL0
A0
A2
VW1/RW1
VL1/RL1
VH1/RH1
SDA
VSS
DIP/SOIC
1 20
2 19
3 18
4 17
5 X9221A 16
6 15
7 14
8 13
9 12
10 11
VCC
RES
RES
RES
A1
A3
SCL
RES
RES
RES
2 FN8163.2
August 30, 2006


Features ® X9221A 64 Taps, 2-Wire Serial Bus Da ta Sheet August 30, 2006 FN8163.2 Dual Digitally Controlled Potentiometer (XD CP™) FEATURES • Two XDCPs in one pa ckage • 2-wire serial interface • R egister oriented format, 8 registers to tal —Directly write wiper position Read wiper position —Store as many a s four positions per pot • Instructio n format —Quick transfer of register contents to resistor array • Direct w rite cell —Endurance–100,000 writes per bit per register • Resistor arra y values —2kΩ, 10kΩ, 50kΩ • Reso lution: 64 taps each pot • 20 Ld plas tic DIP and 20 Ld SOIC packages • Pb- free plus anneal available (RoHS compli ant) BLOCK DIAGRAM DESCRIPTION The X92 21A integrates two digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digit ally controlled potentiometer is implem ented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array i.
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