X9260 Potentiometers Datasheet

X9260 Datasheet, PDF, Equivalent


Part Number

X9260

Description

Dual Digitally-Controlled Potentiometers

Manufacture

Intersil Corporation

Total Page 23 Pages
Datasheet
Download X9260 Datasheet


X9260
®
Data Sheet
X9260
Dual Supply/Low Power/256-Tap/SPI bus
August 29, 2006
FN8170.3
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
Wiper Resistance, 100Ω typical @ V+ = 5V,
V- = -5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current <5µA Max
• VCC: 2.7V to 5.5V Operation
50kΩ, 100kΩ Versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24 Ld SOIC
• Low Power CMOS
www.DataSheet4U.com Power Supply VCC = 2.7V to 5.5V
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
• Pb-Free Plus Anneal Available (RoHS Compliant)
FUNCTIONAL DIAGRAM
DESCRIPTION
The X9260 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four nononvolatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the
contents of the default Data Register (DR0) to the
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
VCC
V+
RH0
RH1
SPI
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power-on Recall
Wiper Counter
Registers (WCR)
Data Registers
(DR0-DR3)
VSS
V- RW0 RL0 RW1 RL1
50kΩ or 100kΩ versions
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners

X9260
X9260
Ordering Information
PART NUMBER
X9260TS24I
PART
MARKING
X9260TS I
POTENTIOMETER
ORGANIZATION TEMPERATURE
VCC LIMITS (V)
(kΩ)
RANGE (°C)
PACKAGE
5 ±10%
100 -40 to +85 24 Ld SOIC (300 mil)
PKG. DWG. #
M24.3
X9260TS24IZ (Note) X9260TS ZI
-40 to +85
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9260US24
X9260US
50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9260US24Z (Note) X9260US Z
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9260TS24I-2.7
X9260TS G
2.7 to 5.5
100
-40 to +85 24 Ld SOIC (300 mil) M24.3
X9260TS24IZ-2.7 (Note) X9260TS ZG
-40 to +85
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9260US24-2.7
X9260US F
50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9260US24Z-2.7 (Note) X9260US ZF
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DETAILED FUNCTIONAL DIAGRAM
RH0 RL0RW0
HOLD
CS
SCK
SO
SI
A0
A1
WP
VCC
V+
INTERFACE
AND
CONTROL
CIRCUITRY
8
Data
Power-on
Recall
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Pot 0
50KΩ and 100KΩ
256-taps
Power-on
Recall
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VSS V-
RL1 RH1 RW1
2 FN8170.3
August 29, 2006


Features ® X9260 Dual Supply/Low Power/256-Tap/ SPI bus Data Sheet August 29, 2006 FN81 70.3 Dual Digitally-Controlled (XDCP ) Potentiometers FEATURES • Dual–T wo Separate Potentiometers • 256 Resi stor Taps/pot–0.4% Resolution • SPI Serial Interface for Write, Read, and Transfer Operations of the Potentiomete r • Wiper Resistance, 100Ω typical @ V+ = 5V, V- = -5V • 4 Nonvolatile Da ta Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Sa ved Wiper Position on Power-up. • Sta ndby Current <5µA Max • VCC: 2.7V to 5.5V Operation • 50kΩ, 100kΩ Versi ons of End to End Resistance • 100 yr . Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 24 Ld SOIC • Low Power CMOS www.DataS heet4U.com • Power Supply VCC = 2.7V to 5.5V V+ = 2.7V to 5.5V V- = -2.7V to -5.5V • Pb-Free Plus Anneal Availabl e (RoHS Compliant) FUNCTIONAL DIAGRAM V CC V+ DESCRIPTION The X9260 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS i.
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