Controlled Potentiometers. X9400 Datasheet

X9400 Datasheet PDF, Equivalent


Part Number

X9400

Description

Quad Digitally Controlled Potentiometers

Manufacture

Intersil Corporation

Total Page 19 Pages
PDF Download
Download X9400 Datasheet PDF


X9400 Datasheet
®
Data Sheet
X9400
Low Noise/Low Power/SPI Bus
July 28, 2006
FN8189.3
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA max
System
Analog
VV+C/VC::2-.75VV
to
to
5.5V
+5V
operation
• 10k, 2.5kend to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
www.DataSheet4U.com Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Pot 0
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW3/RW3
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X9400 Datasheet
X9400
Ordering Information
PART NUMBER
X9400WS24*
PART
MARKING
X9400WS
POTENTIOMETER TEMPERATURE
VCC LIMITS ORGANIZATION
(V) (k)
RANGE
(°C)
PACKAGE
5 ±10%
10
0 to +70
24 Ld SOIC (300 mil)
PKG. DWG. #
M24.3
X9400WS24ZT1
(Note)
X9400WS24I*
X9400WS24IZ*
(Note)
X9400WV24*
X9400WV24I*
X9400WV24IZ*
(Note)
X9400WS Z
X9400WS I
X9400WS ZI
X9400WV
X9400WV I
X9400WV ZI
0 to +70
-40 to +85
-40 to +85
24 Ld SOIC (300 mil) (Pb-free)
Tape and Reel
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
M24.3
M24.3
M24.3
0 to +70
-40 to +85
-40 to +85
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
MDP0044
MDP0044
X9400WV24Z*
(Note)
X9400YS24*
X9400YS24I*
X9400YV24*
X9400YV24I*
X9400YV24IZ*
(Note)
X9400YV24Z*
(Note)
X9400WS24-2.7*
X9400WV Z
X9400YS
X9400YS I
X9400YV
X9400YV I
X9400YV ZI
X9400YV Z
X9400WS F
2.7 to 5.5
2.5
10
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
0 to +70
-40 to +85
0 to +70
-40 to +85
-40 to +85
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-free)
M24.3
M24.3
MDP0044
MDP0044
MDP0044
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9400WS24I-2.7* X9400WS G
X9400WS24IZ-2.7* X9400WS ZG
(Note)
X9400WV24-2.7* X9400WV F
X9400WV24I-2.7* X9400WV G
X9400WV24IZ-2.7* X9400WV ZG
(Note)
X9400WV24Z-2.7* X9400WV ZF
(Note)
-40 to +85
-40 to +85
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
M24.3
M24.3
0 to +70
-40 to +85
-40 to +85
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-free)
MDP0044
MDP0044
MDP0044
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400YS24-2.7* X9400YS F
X9400YS24I-2.7* X9400YS G
X9400YV24-2.7* X9400YV F
X9400YV24I-2.7* X9400YV G
X9400YV24IZ-2.7* X9400YV ZG
(Note)
2.5
0 to +70
24 Ld SOIC (300 mil)
M24.3
-40 to +85 24 Ld SOIC (300 mil)
M24.3
0 to +70
24 Ld TSSOP (4.4mm)
MDP0044
-40 to +85 24 Ld TSSOP (4.4mm)
MDP0044
-40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400YV24Z-2.7* X9400YV ZF
(Note)
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2 FN8189.3
July 28, 2006


Features Datasheet pdf ® X9400 Low Noise/Low Power/SPI Bus Da ta Sheet July 28, 2006 FN8189.3 Quad D igitally Controlled Potentiometers (XDC P™) FEATURES • Four potentiometers per package • 64 resistor taps • SP I serial interface for write, read, and transfer operations of the potentiomet er • Wiper resistance, 40Ω typical at 5V. • Four non-volatile data regis ters for each potentiometer • Non-vol atile storage of multiple wiper positio n • Power-on recall. Loads saved wipe r position on power-up. • Standby cur rent < 1µA max • System VCC: 2.7V to 5.5V operation • Analog V+/V–: -5V to +5V • 10kΩ, 2.5kΩ end to end resistance • 100 yr. data retention Endurance: 100,000 data changes per bit per register • Low power CMOS • 24 Ld SOIC and 24 Ld TSSOP www.DataShe et4U.com • Pb-free plus anneal availa ble (RoHS compliant) BLOCK DIAGRAM VCC VSS V+ VHOLD CS SCK SO SI A0 A1 WP Inte rface and Control Circuitry Data R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 R0 R1 Pot 0 Wiper Counter Register (WCR) DESCRIPTION The.
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