X9525 Memory Datasheet

X9525 Datasheet, PDF, Equivalent


Part Number

X9525

Description

EEPROM Memory

Manufacture

Intersil Corporation

Total Page 24 Pages
Datasheet
Download X9525 Datasheet


X9525
X9525NOTPRXO9ES5CS8O2IBM0L,MEISESLN2UD2BE3S2®DT6FI,TIOSURLT2END2EFP3aWi2Rtb9aOe,DrDSXECUh9S5heCI2GaeT0ntNnSel/Gigabit
Ethernet
Laser Diode Control
January 3, 2006
for
Fiber
Optic Modules
FN8210.1
Dual DCP, EEPROM Memory
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
—256 Tap - 50kΩ
— Non-Volatile
—Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block
LockTM
• Device ID Addressability
• 2-Wire Industry Standard Serial Interface
—Complies to the Gigabit Interface Converter
(GBIC) specification
— Addressable
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• Package
—20 Pin TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9525 combines two Digitally Controlled Potentiom-
eters (DCP’s), and integrated EEPROM with Block
Lock™ protection. All functions of the X9525 are
accessed by an industry standard 2-Wire serial interface.
The DCP’s of the X9525 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.
The features of the X9525 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gi-
gabit Interface Converter (GBIC) specification. The inte-
gration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.
BLOCK DIAGRAM
www.DataSheet4U.com
WP
SDA
SCL
Ao
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
8
PROTECT
LOGIC
CONSTAT
REGISTER
4
2kbit
EEPROM
ARRAY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
RH1
RW1
RL1
RH2
RW2
RL2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2001 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X9525
X9525
Ordering Information
PART
TEMP
PART NUMBER MARKING RANGE (°C)
PACKAGE
X9525V20I
X9525VI
-40 to +85 20 Ld TSSOP
X9525V20IZ
X9525VZI
-40 to +85 20 Ld TSSOP
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PIN CONFIGURATION
20 Pin TSSOP
RH2
RW2
RL2
NC
NC
A0
WP
SCL
SDA
VSS
1
2
3
4
5
6
7
8
9
10
20 VCC
19 NC
18 NC
17 NC
16 NC
15 NC
14 NC
13 RH1
12 RW1
11 RL1
NOT TO SCALE
PIN ASSIGNMENT
Pin Name
1 RH2
2 Rw2
3 RL2
6 A0
7 WP
8 SCL
9
10
11
12
13
20
4, 5, 14, 15,
16, 17, 18,
19
SDA
Vss
RL1
RW1
RH1
VCC
NC
Function
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
Physical Device Address input. A match in the slave address serial data stream, and the Physical De-
vice Address input pin must be in order to initiate communication with the X9525. A maximum of two
(2) devices may occupy the same 2-wire serial bus.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection
is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT
[0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the
wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an
internal “pull-up” resistor, thus if left floating the write protection feature is enabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up
resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Supply Voltage.
No Connect
2 FN8210.1
January 3, 2006


Features NS ESI G D NEW DChannel/Gigabit CT Ether net Laser Diode Control for Fiber Optic Modules FOR Fiber O U 0 R D P E ND TE 952 E U X T M , I 9 T S OM 232 Sheet Ja nuary 3, 2006 FN8210.1 SU B RE C SL2Dat a NOT SSIBLE 22326, I O L P S 20, I X95 8 ® X9525 Dual DCP, EEPROM Memory FE ATURES • Two Digitally Controlled Pot entiometers (DCP’s) —100 Tap - 10k —256 Tap - 50kΩ —Non-Volatile Write Protect Function • 2kbit EEPRO M Memory with Write Protect & Block Loc kTM • Device ID Addressability • 2- Wire Industry Standard Serial Interface —Complies to the Gigabit Interface C onverter (GBIC) specification —Addres sable • Single Supply Operation —2. 7V to 5.5V • Hot Pluggable • Packag e —20 Pin TSSOP • Pb-Free Plus Anne al Available (RoHS Compliant) www.DataS heet4U.com DESCRIPTION The X9525 combi nes two Digitally Controlled Potentiome ters (DCP’s), and integrated EEPROM w ith Block Lock™ protection. All funct ions of the X9525 are accessed by an industry standard 2-Wire serial interface. The DCP’s of the X9525 m.
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