X98024 Digitizer Datasheet

X98024 Datasheet, PDF, Equivalent


Part Number

X98024

Description

240MHz Triple Video Digitizer

Manufacture

Intersil Corporation

Total Page 29 Pages
Datasheet
Download X98024 Datasheet


X98024
NTOHTERISELC9OI8MM0P0M1RE-O2N4VD0EEIDSDAAFLO1T®R0E0RN%NECAWOTDDIMVaEEPtSaAIGTSINhBSeLeE-t
240MHz Triple Video Digitizer with
Digital PLL
The X98024 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 240MSPS conversion
rate supports resolutions up to WUXGA at 75Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
To minimize noise, the X98024's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 240MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™) eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
The X98024's digital PLL generates a pixel clock from the
analogwww.DataSheet4U.com source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 240MHz
with sampling clock jitter of 250ps peak to peak.
Simplified Block Diagram
March 8, 2006
X98024
FN8220.3
Features
• 240MSPS maximum conversion rate
• Low PLL clock jitter (250ps p-p @ 240MSPS)
• 64 interpixel sampling positions
• 0.35Vp-p to 1.4Vp-p video input range
• Programmable bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel sync detection
• 1.15W typical PD @ 240MSPS
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
RGB/YPbPrIN 1
RGB/YPbPrIN 2
3
3
Voltage
Clamp
PGA
Offset
DAC
ABLC™
+ 8 bit ADC
SOGIN1/2
HSYNCIN1/2
VSYNCIN1/2
Sync
Processing
Digital PLL
AFE Configuration and Control
8 or 16
RGB/YUVOUT
x3
HSYNCOUT
VSYNCOUT
HSOUT
PIXELCLKOUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X98024
X98024
Ordering Information
PART NUMBER
PART MARKING
MAXIMUM PIXEL
RATE
TEMP RANGE
(°C)
PACKAGE
X98024L128-3.3
X98024L-3.3
240MHz
0 to 70
128 MQFP
X98024L128-3.3-Z (See Note)
X98024L-3.3Z
240MHz
0 to 70
128 MQFP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
RIN1
RIN2
GIN1
RGBGND1
GIN2
RGBGND2
BIN1
BIN2
VCLAMP
VIN+
VIN- PGA
VCLAMP
VIN+
VIN- PGA
VCLAMP
VIN+
VIN- PGA
Offset 10
DAC
ABLC™
+ 8 bit ADC
Offset 10
DAC
ABLC™
+ 8 bit ADC
Offset 10
DAC
ABLC™
+ 8 bit ADC
8
8
8
SOGIN1
SOGIN2
HSYNCIN1
HSYNCIN2
VSYNCIN1
VSYNCIN2
CLOCKINV
XTALIN
XTALOUT
SCL
SDA
SADDR
Sync
Processing
Digital PLL
Serial
Interface
AFE Configuration
and Control
8 RP[7:0]
8 RS[7:0]
8 GP[7:0]
8 GS[7:0]
8 BP[7:0]
8 BS[7:0]
DATACLK
DATACLK
HSOUT
VSOUT
HSYNCOUT
VSYNCOUT
XTALCLKOUT
2 FN8220.3
March 8, 2006


Features NS ESIG LE D EW TI B O R N C O M PA F D E E ND 100% IVE Sheet OMM 240 IS A ERNA TData C E R T 1 L NOT SL9800 VED A I O T HE I M PR ® X98024 March 8, 2006 FN 8220.3 240MHz Triple Video Digitizer w ith Digital PLL The X98024 3-channel, 8 -bit Analog Front End (AFE) contains al l the components necessary to digitize analog RGB or YUV graphics signals from personal computers, workstations and v ideo set-top boxes. The fully different ial analog design provides high PSRR an d dynamic performance to meet the strin gent requirements of the graphics displ ay industry. The AFE’s 240MSPS conver sion rate supports resolutions up to WU XGA at 75Hz refresh rate, while the fro nt end's high input bandwidth ensures s harp images at the highest resolutions. To minimize noise, the X98024's analog section features 2 sets of pseudo-diff erential RGB inputs with programmable i nput bandwidth, as well as internal DC restore clamping (including mid-scale c lamping for YUV signals). This is followed by the programmable gai.
Keywords X98024, datasheet, pdf, Intersil Corporation, 240MHz, Triple, Video, Digitizer, 98024, 8024, 024, X9802, X980, X98, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)