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DM54LS73A Dataheets PDF



Part Number DM54LS73A
Manufacturers National Semiconductor
Logo National Semiconductor
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
Datasheet DM54LS73A DatasheetDM54LS73A Datasheet (PDF)

DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and.

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DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs Connection Diagram Dual-In-Line Package www.DataSheet4U.com TL F 6372 – 1 Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN See NS Package Number J14A M14A N14A or W14B Function Table Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Q L Q0 H L Toggle Q0 Q0 Outputs Q H Q0 L H v v v v H H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level v e Negative going edge of pulse Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse C1995 National Semiconductor Corporation TL F 6372 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C DM54LS DM74LS 0 C to a 70 C b 65 C to a 150 C Storage Temperature Range Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Clock High Preset Low Clear Low tW Pulse Width (Note 3) Clock High Preset Low Clear Low tSU tSU tH tH TA Setup Time (Notes 1 and 2) Setup Time (Notes 1 and 3) Hold Time (Notes 1 and 2) Hold Time (Notes 1 and 3) Free Air Operating Temperature 0 0 20 25 25 25 30 30 20v 25v 0v 5v b 55 DM54LS73A Nom 5 Max 55 Min 4 75 2 07 b0 4 DM74LS73A Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA MHz MHz 4 30 25 0 0 20 25 25 25 30 30 2.


X9C303 DM54LS73A FDS6298


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