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AS5SS256K36 Dataheets PDF



Part Number AS5SS256K36
Manufacturers Austin Semiconductor
Logo Austin Semiconductor
Description 256K x 36 SSRAM Flow-Through Synchronous Burst SRAM
Datasheet AS5SS256K36 DatasheetAS5SS256K36 Datasheet (PDF)

Austin Semiconductor, Inc. 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM FEATURES ! ! ! ! ! ! ! AS5SS256K36 & AS5SS256K36A PIN ASSIGNMENT (Top View) SSRAM ! ! ! ! ! ! Organized 256K x 36 Fast Clock and OE\ access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered a.

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Austin Semiconductor, Inc. 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM FEATURES ! ! ! ! ! ! ! AS5SS256K36 & AS5SS256K36A PIN ASSIGNMENT (Top View) SSRAM ! ! ! ! ! ! Organized 256K x 36 Fast Clock and OE\ access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-lead TQFP package for high density, high speed Low capacitive bus loading 100-pin TQFP (DQ) (2-chip enable version, “A” indicator) SA SA ADV\ ADSP\ ADSC\ OE\ BWE\ GW\ CLK Vss VDD SA BWa\ BWb\ BWc\ BWd\ CE2 CE\ SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 OPTIONS www.DataSheet4U.com MARKING -8.5* -10 DQ No. 1001 A (PRELIMINARY) no indicator XT* IT Timing 8.5ns/10ns/100MHz 10ns/15ns/66MHz ! Packages 100-pin TQFP (2-chip enable) ! Pinout 2-chip Enables 3-chip Enables ! Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) ! DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb V DDQ Vss DQb DQb DQb DQb Vss V DDQ DQb DQb Vss NC V DD ZZ DQa DQa V DDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa 100-pin TQFP (DQ) (3-chip enable version, no indicator) SA SA ADV\ ADSP\ ADSC\ OE\ BWE\ GW\ CLK Vss VDD CE2\ BWa\ BWb\ BWc\ BWd\ CE2 CE\ SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SA SA SA SA SA SA SA NF NF VDD Vss DNU DNU SA0 SA1 SA SA SA SA MODE *NOTE: -8.5/XT combination not available. GENERAL DESCRIPTION The AS5SS256K36 employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. This 8Mb Synchronous Burst SRAM integrates a 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). Note that CE2\ is not available on the A version. DQPc DQc DQc VDD Q Vss DQc DQc DQc DQc Vss VDD Q DQc DQc Vss V DD NC Vss DQd DQd VDD Q Vss DQd DQd DQd DQd Vss VDD Q DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 For more products and information please visit our web site at www.austinsemiconductor.com AS5SS256K36 & AS5SS256K36A Rev. 3.5 2/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SA SA SA SA SA SA SA SA NF VDD Vss DNU DNU SA0 SA1 SA SA SA SA MODE 1 Austin Semiconductor, Inc. GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable (OE\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also asynchronous. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\) or address status controller (ADSC\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\). Address and write control are registered on-chip to AS5SS256K36 & AS5SS256K36A SSRAM simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa\ controls DQa’s and DQPa; BWb\ controls DQb’s and DQPb; BWc\ controls DQc’s and DQPc; BWd\ controls DQd’s and DQPd. GW\ LOW causes all bytes to be written. Parity bits are also featured on this device. This 8Mb Synchronous Burst SRAM operates from a +3.3V VDD power supply, and all inputs and outputs are TTLcompatible. The device is ideally suited for 486, Pentium©, 680x0 and PowerPCTM systems and those systems that benefit from a wide synchronous data bus. FUNCTIONAL BLOCK DIAGRAM 18 SA0, SA1, SAs MODE ADV\ CLK ADDRESS REGISTER 18 SA0-SA1 16 18 BINARY COUNTER AND LOGIC CL Q1 S.


AS5SS256K18 AS5SS256K36 AS5SS256K36A


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