5V 256K x 8/128K x 8 CMOS FLASH EEPROM
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• Organization: 256K×8 or 128K×16 • Se...
Description
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Organization: 256K×8 or 128K×16 Sector architecture - One 16K; two 8K; one 32K; and three 64K byte sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip Single 5.0±0.5V power supply for read/write operations Sector protection High speed 55/70/90/120 ns address access time Automated on-chip programming algorithm - Automatically programs/verifies data at specified address Automated on-chip erase algorith - Automatically preprograms/erases chip or specified sectors 10,000 write/erase cycle endurance Hardware RESET pin - Resets internal state machine to read mode Low power consumption - 20 mA typical read current - 30 mA typical program current - 300 µA typical standby current - 1 µA typical standby current (RESET = 0) JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - RY/BY output Erase suspend/resume - Supports reading data from a sector not being erased Low VCC write lock-out below 2.8V
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48-pin TSOP
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC NC A7 A6 A5 A4 A3 A2 A1
44-pin SO
RY/BY VCC VSS RESET Program/erase control Command register CE OE A-1
Sector protect switches Erase voltage generator
DQ0–DQ15
Input/output buffers
Program voltage...
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