W3EG6466S-AD4

White Electronic Designs W3EG6466S-AD4 -BD4 PRELIMINARY* 512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DDR200, DDR266 and DDR333 JEDEC design specifications Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.20V www.DataSheet4U.com DESCRIPTION The W3EG6466S is a 2x32Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of sixteen 32Mx8 components as eight 64Mx8 stacked DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. JEDEC standard 200 pin SO-DIMM package Package height options: AD4: 35.5mm (1.38") BD4: 31.75mm (1.25") NOTE: Consult factory for availability of: RoHS compliant products Vendor source control options Industrial temperature option OPERATING FREQUENCIES DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @C...