W3EG72128S-JD3

White Electronic Designs 1GB – 2x64Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data rate architecture DDR200, DDR266, DDR333 and DDR400 JEDEC design specifications BI-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC = VCCQ = +2.5V ± 0.20V (100, 133, 166MHz) www.DataSheet4U.com W3EG72128S-D3 -JD3 ADVANCED* DESCRIPTION the W3EG72128S is a 2x64Mx72 Double data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precisse cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. VCC = VCCQ = +2.6V ± 0.10V (200MHz) JEDEC Standard 184 pin DIMM package PCB height: 30.48 (1.20") NOTE: Consult factory for availability of: RoHS compliant products Vendor source control options Industrial temperature option OPERATING FREQUENCIES DDR400 @CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DD...