CY28341

CY28341 Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems Features Supports VIA P4M266/KM266 chipsets Supports Pentium® 4, Athlon™ processors Supports two DDR DIMMS Supports three SDRAMS DIMMS at 100 MHz Provides: — Two different programmable CPU clock pairs — Six differential SDRAM DDR pairs — Three low-skew/low-jitter AGP clocks — Seven low-skew/low-jitter PCI clocks — One 48M output for USB — One programmable 24M or 48M for SIO Dial-a-Frequency™ and Dial-a-dB features Spread Spectrum for best electromagnetic interference (EMI) reduction Watchdog feature for systems recovery SMBus-compatible for programmability 56-pin SSOP and TSSOP packages Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1100 1111 CPU 66.80 100.00 120.00 133.33 72.00 105.00 160.00 140.00 77.00 110.00 180.00 150.00 90.00 100.00 200.00 133.33 AGP 66.80 66.80 60.00 66.67 72.00 70.00 64.00 70.00 77.00 73.33 60.00 60.00 60.00 66.67 66.67 66.67 PCI 33.40 33.40 30.00 33.33 36.00 35.00 32.00 35.00 38.50 36.67 30.00 30.00 30.00 33.33 33.33 33.33 Block Diagram www.DataSheet4U.com Pin Configuration[1] VDDR REF(0:1) REF0 VDDI CPUCS_T/C FS0 XIN XOUT XTAL SELP4_K7# VDDC CPU(0:1)/CPU0D_T/C VDDPCI FS2 PLL1 FS3 FS1 PCI(3:6) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M 48M /2 PD# SDATA SCLK SMBus PLL2 WDEN 24_48M WD SELSDR_DDR Buf_IN S2D CONVERT SRESET# VDDD FBOUT DDRT(0:5)/SDRAM(0,2,4,6,8,10) DDRC(0:...