Synchronous DRAM. HYB39S256160CTL Datasheet

HYB39S256160CTL DRAM. Datasheet pdf. Equivalent

HYB39S256160CTL Datasheet
Recommendation HYB39S256160CTL Datasheet
Part HYB39S256160CTL
Description (HYB39S256xxxCT) 256 MBit Synchronous DRAM
Feature HYB39S256160CTL; HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: .
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Datasheet
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Infineon Technologies HYB39S256160CTL
256 MBit Synchronous DRAM
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
High Performance:
-7.5 -8 Units
fCK 133 125 MHz
tCK3 7.5
8
ns
tAC3 5.4
6
ns
tCK2 10 10
ns
tAC2 6 6 ns
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
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Programmable Burst Length:
1, 2, 4, 8
Full page burst length for
sequential wrap around
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.17 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
INFINEON Technologies
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Infineon Technologies HYB39S256160CTL
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Ordering Information
Type
Speed Grade
Package
Description
HYB 39S256400CT-7.5
HYB 39S256400CT-8
HYB 39S256800CT-7.5
HYB 39S256800CT-8
HYB 39S256160CT-7.5
HYB 39S256160CT-8
HYB39S256xx0CTL
PC133-333-520
PC100-222-620
PC133-333-520
PC100-222-620
PC133-333-520
PC100-222-620
PC100-xxx-620
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
133MHz 4B x 16M x 4 SDRAM
125MHz 4B x 16M x 4 SDRAM
133MHz 4B x 8M x 8 SDRAM
125MHz 4B x 8M x 8 SDRAM
133MHz 4B x 4M x 16 SDRAM
125MHz 4B x 4M x 16 SDRAM
Low Power Versions (on request)
:Pin Description
CLK
CKE
Clock Input
Clock Enable
DQx
DQM, LDQM, UDQM
Data Input /Output
Data Mask
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CS
RAS
CAS
WE
A0-A12
BA0, BA1
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
VDD
VSS
VDDQ
VSSQ
NC
Power (+3.3V)
Ground
Power for DQs (+ 3.3V)
Ground for DQs
not connected
INFINEON Technologies
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Infineon Technologies HYB39S256160CTL
Pinouts
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
16 M x 16
32 M x 8
64 M x 4
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VDD
DQ0
VDD
DQ0
VDD
N.C.
VDDQ
DQ1
VDDQ
N.C.
VDDQ
N.C.
DQ2 DQ1 DQ0
VSSQ
DQ3
VSSQ
N.C.
VSSQ
N.C.
DQ4 DQ2 N.C.
VDDQ
DQ5
VDDQ
N.C.
VDDQ
N.C.
DQ6 DQ3 DQ1
VSSQ
DQ7
VSSQ
N.C.
VSSQ
N.C.
VDD
VDD
LDQM N.C.
VDD
N.C.
WE WE WE
CAS CAS CAS
RAS RAS RAS
CS CS CS
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS VSS VSS
53 N.C. DQ7 DQ15
52
VSSQ
VSSQ
VSSQ
51 N.C. N.C. DQ14
50 DQ3 DQ6 DQ13
49
VDDQ
VDDQ
VDDQ
48 N.C. N.C. DQ12
47 N.C. DQ5 DQ11
46
VSSQ
VSSQ
VSSQ
45 N.C. N.C. DQ10
44 DQ2 DQ4 DQ9
43
VDDQ
VDDQ
VDDQ
42 N.C. N.C. DQ8
41 VSS VSS VSS
40 N.C. N.C. N.C.
39 DQM DQM UDQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
SPP04126
Pinout for x4, x8 & x16 organised 256M-DRAMs
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