16R6DC PAL16R6DC Datasheet pdf - PAL16R6DC. Equivalent, Catalog

FINAL

COM’L: -4/5/7/B/B-2/A, D/2

PAL16R8 Family

20-Pin TTL Programmable Array Logic

Advanced

Micro

Devices

DISTINCTIVE CHARACTERISTICS

s As fast as 4.5 ns maximum propagation delay

s Popular 20-pin architectures: 16L8, 16R8, 16R6,

16R4

s Programmable replacement for high-speed TTL

logic

s Register preload for testability

s Power-up reset for initialization

s Extensive third-party software and programmer

support through FusionPLD partners

s 20-Pin DIP and PLCC packages save space

s 28-Pin PLCC-4 package provides ultra-clean

high-speed signals

www.DataSheet4U.com

GENERAL DESCRIPTION

The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6,

PAL16R4) includes the PAL16R8-5/4 Series which pro-

vides the highest speed in the 20-pin TTL PAL device

family, making the series ideal for high-performance ap-

plications. The PAL16R8 Family is provided with stan-

dard 20-pin DIP and PLCC pinouts and a 28-pin PLCC

pinout. The 28-pin PLCC pinout contains seven extra

ground pins interleaved between the outputs to reduce

noise and increase speed.

The devices provide user-programmable logic for re-

placing conventional SSI/MSI gates and flip-flops at a

reduced chip count.

The family allows the systems engineer to implement

the design on-chip, by opening fuse links to configure

AND and OR gates within the device, according to the

desired logic function. Complex interconnections be-

tween gates, which previously required time-consuming

layout, are lifted from the PC board and placed on sili-

con, where they can be easily modified during proto-

typing or production.

The PAL device implements the familiar Boolean logic

transfer function, the sum of products. The PAL device

is a programmable AND array driving a fixed OR array.

The AND array is programmed to create custom product

terms, while the OR array sums selected terms at the

outputs.

In addition, the PAL device provides the following

options:

— Variable input/output pin ratio

— Programmable three-state outputs

— Registers with feedback

Product terms with all connections opened assume the

logical HIGH state; product terms connected to both true

and complement of any single input assume the logical

LOW state. Registers consist of D-type flip-flops that are

loaded on the LOW-to-HIGH transition of the clock. Un-

used input pins should be tied to VCC or GND.

The entire PAL device family is supported by the

FusionPLD partners. The PAL family is programmed on

conventional PAL device programmers with appropriate

personality and socket adapter modules. Once the PAL

device is programmed and verified, an additional con-

nection may be opened to prevent pattern readout. This

feature secures proprietary circuits.

PRODUCT SELECTOR GUIDE

Device

PAL16L8

PAL16R8

PAL16R6

PAL16R4

Dedicated

Inputs

Outputs

6 comb.

2 comb.

8 reg.

6 reg.

2 comb.

4 reg.

4 comb.

Publication# 16492 Rev. D Amendment /0

Issue Date: February 1996

Product Terms/

Output

Feedback

I/O

–

reg.

I/O

reg.

I/O

Enable

prog.

2-3

PAL16R6DC. 16R6DC Datasheet

16R6DC PAL16R6DC. Datasheet pdf. Equivalent