PI74SSTVF16859

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74SSTVF16859 13-Bit to 26-Bit Registered Buffer Product Features PI74 SSTVF16859 is designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 Supports SSTL_2 Class I specifications on outputs All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. Designed for DDR Memory Flow-Through Architecture Packages: 64-pin, 240-mil wide plastic TSSOP (A) 56-pin, Plastic Very Thin Fine Pitch Quad Flat No Lead QFN (ZB) Product Description Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock (CLK and CLK). Data registered at the crossing of CLK going HIGH, and CLK going LOW. The PI74SSTVF16859 supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS R...