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AT24C256B Dataheets PDF



Part Number AT24C256B
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description Two-wire Serial EEPROM
Datasheet AT24C256B DatasheetAT24C256B Datasheet (PDF)

Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) • Internally Organized as 32,768 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability – Endurance: One Million.

  AT24C256B   AT24C256B


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Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) • Internally Organized as 32,768 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability – Endurance: One Million Write Cycles – Data Retention: 40 Years • Lead-free/Halogen-free Devices Available • 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages • Die Sales: Wafer Form, Waffle Pack and Bumped Wafers Two-wire Serial EEPROM 256K (32,768 x 8) AT24C256B Description The AT24C256B provides 262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin SAP, 8lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (1.8V to 5.5V) version. Not Recommended for New Design Pin Configurations 8-lead PDIP 8-lead SOIC Pin Name A0–A2 SDA SCL WP GND Function Address Inputs Serial Data Serial Clock Input Write Protect Ground A0 A1 A2 GND 1 2 3 4 8 VCC A0 7 WP A1 6 SCL A2 5 SDA GND 1 2 3 4 8 VCC 7 WP 6 SCL 5 SDA 8-lead dBGA2 VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 A2 4 GND 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 VCC 7 WP 6 SCL 5 SDA Bottom View 8-lead Ultra Thin SAP VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 A2 4 GND Bottom View Rev. 5279C–SEEPR–3/09 1. Absolute Maximum Ratings* Operating Temperature  55C to +125C Storage Temperature 65C to +150C Voltage on Any Pin with Respect to Ground  1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1-1. Block Diagram VCC GND WP SCL SDA A2 A1 A0 START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR SERIAL CONTROL EN H.V. PUMP/TIMING LOGIC COMP LOAD INC DATA RECOVERY R/W DATA WORD ADDR/COUNTER EEPROM X DEC DIN DOUT Y DEC SERIAL MUX DOUT/ACK LOGIC 2 AT24C256B 5279C–SEEPR–3/09 AT24C256B 2. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. 3. Memory Organization AT24C256B, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each. Random word addressing requires a 15-bit data word address. Table 3-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V Symbol Te.


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