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ATA5760 Dataheets PDF



Part Number ATA5760
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description (ATA5760 / ATA5761) UHF ASK/FSK Receiver
Datasheet ATA5760 DatasheetATA5760 Datasheet (PDF)

Features • Two Different IF Receiving Bandwidth Versions Are Available • • • • • • • • • • • • • • • (BIF = 300 kHz or 600 kHz) Frequency Receiving Range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz 30 dB Image Rejection Receiving Bandwidth BIF = 600 kHz for Low Cost 90-ppm Crystals and BIF = 300 kHz for 55 ppm Crystals Fully Integrated LC-VCO and PLL Loop Filter Very High Sensitivity with Power Matched LNA High System IIP3 (–16 dBm), System 1-dB Compression Point (–25 dBm) High Large-s.

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Features • Two Different IF Receiving Bandwidth Versions Are Available • • • • • • • • • • • • • • • (BIF = 300 kHz or 600 kHz) Frequency Receiving Range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz 30 dB Image Rejection Receiving Bandwidth BIF = 600 kHz for Low Cost 90-ppm Crystals and BIF = 300 kHz for 55 ppm Crystals Fully Integrated LC-VCO and PLL Loop Filter Very High Sensitivity with Power Matched LNA High System IIP3 (–16 dBm), System 1-dB Compression Point (–25 dBm) High Large-signal Capability at GSM Band (Blocking –30 dBm at +20 MHz, IIP3 = –12 dBm at +20 MHz) 5V to 20V Automotive Compatible Data Interface Data Clock Available for Manchester- and Bi-phase-coded Signals Programmable Digital Noise Suppression Low Power Consumption Due to Configurable Polling Temperature Range –40°C to +105°C ESD Protection 2 kV HBM, All Pins Communication to Microcontroller Possible Via a Single Bi-directional Data Line Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements UHF ASK/FSK Receiver ATA5760 ATA5761 1. Description www.DataSheet4U.com The ATA5760/ATA5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF transmitter T5750. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. It can be used in the frequency receiving range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz for ASK or FSK data transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz applications. Figure 1-1. System Block Diagram UHF ASK/FSK Remote control receiver UHF ASK/FSK Remote control transmitter T5750 ATA5760/ ATA5761 Demod. PLL IF Amp Control 1...5 µC XTO Antenna VCO Antenna PLL XTO Power amp. LNA VCO 4896C–RKE–04/06 Figure 1-2. Block Diagram CDEM FSK/ASKdemodulator and data filter Rssi Limiter out RSSI IF Dem_out Data interface DATA SENS AVCC AGND DGND DVCC POLLING/_ON Sensitivityreduction Polling circuit and control logic Amp. DATA_CLK 4. Order f0 = 950 kHz/ 1 MHz FE CLK IC_ACTIVE LPF fg = 2.2 MHz Standby logic IF Amp. Loopfilter Poly-LPF fg = 7 MHz LC-VCO XTO XTAL LNAREF f f :2 :256 LNA_IN LNAGND LNA 2 ATA5760/ATA5761 4896C–RKE–04/06 ATA5760/ATA5761 2. Pin Configuration Figure 2-1. Pinning SO20 SENS 1 20 DATA IC_ACTIVE 2 19 CDEM 3 18 DGND AVCC 4 17 DATA_CLK TEST 1 5 16 TEST 4 AGND 6 ATA5760/ ATA5761 15 DVCC NC 7 14 XTAL LNAREF 8 13 NC LNA_IN 9 12 TEST 3 LNAGND 10 11 TEST 2 Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Description Symbol SENS IC_ACTIVE CDEM AVCC TEST 1 AGND NC LNAREF LNA_IN LNAGND TEST 2 TEST 3 NC XTAL DVCC TEST 4 DATA_CLK DGND POLLING/_ON DATA Function Sensitivity-control resistor IC condition indicator: Low = sleep mode, High = active mode Lower cut-off frequency data filter Analog power supply Test pin, during operation at GND Analog ground Not connected, connect to GND High-frequency reference node LNA and mixer RF input DC ground LNA and mixer Do not connect during operating Test pin, during operation at GND Not connected, connect to GND Crystal oscillator XTAL connection Digital power supply Test pin, during operation at DVCC Bit clock of data stream Digital ground Selects polling or receiving mode; Low: receiving mode, High: polling mode Data output/configuration input 3 4896C–RKE–04/06 3. RF Front End The RF front end of the receiver is a low-IF heterodyne configuration that converts the input signal into an about 1 MHz IF signal with an image rejection of typical 30 dB. According to Figure 2-1 on page 3 the front end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier. The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crystal oscillator) generates the reference frequency fXTO. The integrated LC-VCO generates two times the mixer drive frequency fVCO. The I/Q signals for the mixer are generated with a divide by two circuit (fLO = fVCO/2). fVCO is divided by a factor of 256 and feeds into a phase frequency detector and compared with fXTO. The output of the phase frequency detector is fed into an integrated loop filter and thereby generates the control voltage for the VCO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/128 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at pin XTAL. According to Figure 3-1, the crystal should be connected to GND with a series cap.


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