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DL5256 Dataheets PDF



Part Number DL5256
Manufacturers DynaChip
Logo DynaChip
Description (DL5500 Series) The Industry's First Fast Field Programmable Gate Array
Datasheet DL5256 DatasheetDL5256 Datasheet (PDF)

DL5000™ Family Fast Field Programmable Gate Array Features • Fast Field Programmable Gate Arrays™ Patented Active Repeater™ Architecture Data and Clock Rates up to 270 MHz Complex operations up to 200 MHz Input Block Register Setup Time 800 ps Output Block Register Clock-to-out 1.6 ns ECL, PECL and GTL Interface Levels 100K and 100KH Compatible Differential Outputs 1,000 to 10,000 Gates 6 Low-skew Clock Trees Highly Predictable, Fanout Independent Routing Delays • SRAM-based Programming • JTAG B.

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DL5000™ Family Fast Field Programmable Gate Array Features • Fast Field Programmable Gate Arrays™ Patented Active Repeater™ Architecture Data and Clock Rates up to 270 MHz Complex operations up to 200 MHz Input Block Register Setup Time 800 ps Output Block Register Clock-to-out 1.6 ns ECL, PECL and GTL Interface Levels 100K and 100KH Compatible Differential Outputs 1,000 to 10,000 Gates 6 Low-skew Clock Trees Highly Predictable, Fanout Independent Routing Delays • SRAM-based Programming • JTAG Boundary Scan • Fully Automatic Implementation Using DynaTool™ • • • • • • • • • • • DL5 2 PG 20 56 964 1 8 Introduction The DL5000 is the industry’s first Fast Field Programmable Gate Array (FFPGA™) family. Utilizing a breakthrough in field programmable interconnect techniques called Active Repeaters, this family provides unprecedented system level performance. High operating frequencies combined with fast ECL, GTL and PECL input and output structures make these devices ideal for high-speed interfaces, subsystems and core logic. DL5000 family devices are ideal for applications where other FPGAs can not meet performance requirements. They are also ideal for applications where designers want to integrate many discrete ECL devices. Benefits to the user include ultra high-speed, fast time-to-market, reduced risk and maximum design flexibility. The DL5000 features SRAM-based programming allowing the devices to be configured in-circuit and reprogrammed on-the-fly. They can be reconfigured an unlimited number of times providing maximum flexibility for design iterations and field upgrades. Applications Examples www.DataSheet4U.com • Telecommunications and Datacommunications Sonet and ATM Interfaces Satellite Communications FDDI • Test and Instrumentation VLSI and Memory Testers Oscilloscopes and Logic Analyzers • High-Speed Graphics Real-Time Video Imaging HDTV • Servers and Peripherals High-speed Servers High-speed Bus Interfaces Fast Graphics Interfaces • Emulation Gates Device DL5064 DL5256 DL5528 1,250 5,000 10,000 Logic Blocks 64 256 528 Input Blocks 48 76 104 Output Blocks 49 76 112 Flip Flops 212 664 1,272 Clock Trees 6 6 6 Datasheet November 1998 DL5000 - Fast Field Programmable Gate Array Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 High Performance Active Repeater Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Active Repeater Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Input and Output Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input and Output Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Mode Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


DL5528 DL5256 G4PH30KD


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