AD7787

Preliminary Technical Information FEATURES Power Supply: 2.5 V to 5.25 V operation Normal Mode: 75 µA max Power-down Mode: 1 µA max RMS noise: 1.1 µV at 9.5 Hz update rate 19.5-bit p-p resolution (22 bits effective resolution) Integral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection Internal clock oscillator Rail-to-rail input buffer VDD monitor channel Temperature range: –40°C to +105°C 10-lead MSOP GND Low Power, 2-Channel 24-Bit Sigma-Delta ADC AD7787 FUNCTIONAL BLOCK DIAGRAM VDD REFIN AD7787 AIN1(+) AIN1(-) AIN2 MUX BUF Sigma Delta ADC SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS CLOCK Figure 1. GENERAL DESCRIPTION The AD7787 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 24-bit ∑-∆ ADC with one differential input and one single-ended input that can be buffered or unbuffered. The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate from the part is software programmable and can be varied from 9.5 Hz to 120 Hz, with the rms noise equal to 1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduction in the current consumption. The update rate, cutoff frequency, and settling time will scale with the clock frequency. The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipati...