SI5320

Si5320 SONET/SDH PRECISION CLOCK MULTIPLIER IC Features  Ultra-low-jitter clock output with jitter generation as low as 0.3 psRMS  No external components (other than a resistor and standard bypassing)  Input clock ranges at 19, 39, 78, 155, 311, and 622 MHz  Output clock ranges at 19, 155, or 622 MHz  Digital hold for loss of input clock  Support for forward and reverse FEC clock scaling  Selectable loop bandwidth  Loss-of-signal alarm output  Low power  Small size (9x9 mm) Applications  SONET/SDH line/port cards  Optical modules  Core switches  Digital cross connects  Terabit routers Description The Si5320 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-192/OC-48 and 10 GbE. This device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 155, or 622 MHz range. Silicon Laboratories’ DSPLL™ technology delivers all PLL functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. FEC rates are supported with selectable 255/ 238 or 238/255 scaling of the clock multiplication ratios. The Si5320 establishes a new standard in performance and integration for ultra-low-jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram REXT VS...