Document
Freescale Semiconductor Technical Data
Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror
The 908E621 is an integrated single package solution that includes a high performance HC08 microcontroller with a SMARTMOS analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), a 10 bit analog-to-digital converter (ADC), internal serial peripheral interface (SPI), and an internal clock generator module (ICG). The analog control die provides four half-bridge and three high side outputs with diagnostic functions, a Hall effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (LIN) physical layer.
The single package solution, together with LIN, provides optimal application performance adjustments and space saving PCB design. It is well-suited for the control of automotive high end mirrors.
Features
• High performance M68HC908EY16 core • 16 KB of on-chip flash memory, 512 B of RAM • Two 16-bit, two-channel timers • LIN physical layer interface • Autonomous MCU watchdog / MCU supervision • One analog input with switchable current source • Four low RDS(ON) half-bridge outputs • Three low RDS(ON) high side outputs • Wake-up and 2 or 3-pin Hall effect sensor input • 12 microcontroller I/Os • Pb-free packaging designated by suffix codes EK
Document Number: MM908E621 Rev. 6.0, 4/2012
908E621
QUAD HALF-BRIDGE AND TRIPLE HIGH SIDE SWITCH WITH EMBEDDED MCU AND LIN
EK (Pb-Free) 98ASA10712D 54-PIN SOICW-EP
ORDERING INFORMATION
Device (Add an R2 suffix for Tape and reel orders)
Temperature Range (TA)
Package
MM908E621ACPEK
-40 to 85°C 54 SOICW-EP
100 nF
4.7 μF
μC PortA
μC PortB
μC PortC
μC PortD μC PortE
Internally Connected Internally Connected
LIN VSP1:8] VDDA/VREFH
L0
EVDD VDD
HB1
VSSA/VREFL
EVSS VSS
908E621
HB2 HB3
RST A
RST
HB4
IRQ A IRQ
HS1
PTA/KBD0 PTA1/KBD1
HS2
PTA2/KBD2 PTA3/KBD3
HS3
PTA4/KBD4
HVDD
PTB3/AD3
A0
PTB4/AD4 PTB5/AD5
A0CST
PTC2/MCLK
H0
PTC3/OSC2
PTC4/OSC1
TESTMODE
PTD0/TACH0 PTD1/TACH1 PTE1/RXD
EP GND[1:4]
>22 μF Wake-up Input
100 nF
M M 4 x Half-brideOutputs M
High Side Output 1
High Side Output 2
High Side Output 3 Switched 5.0 V Output Analog Input with Curet Source Analog Input Current Source Trim
Two 3-pin Hall Sensor Input
Pull to GND for User Mode
Figure 1. 908E621 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007-2012. All rights reserved.
Analog Integrated Circuit Device Data Freescale Semiconductor
IRQ RST VSSA/VREFL EVSS EVDD VDDA/VREFH
908E621
2
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4
PTB3/AD3 PTB4/AD4 PTB5/AD5 PTC2/MCLK PTC3/OSC2 PTC4/OSC1 PTD1/TACH1
FLSVPP
M68HC08 CPU
CPU Registers
ALU
Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes
Monitor ROM, 310 Bytes
Flash programming (Burn-in), ROM 1024 Bytes
User Flash Vector Space, 36 Bytes
OSC2 Internal Clock OSC1 Generator Module
RST 24 Integral System Integration Module
IRQ Single External IRQ Module
VREFH VDDA VREFL
10 Bit Analog-toDigital Converter
VSSA
Module
VDD VSS
POWER
Power-ON Reset Module
Security Module
PTA6/SS PTA5/SPSCK
PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0
PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 PTB0/AD0
DDRB PORT B
DDRA PORT A
Internal Bus
PORT C PORT D PORT E DDRC DDRD DDRE
Single Breakpoint Break Module
5-Bit Keyboard Interrupt Module
2-channel Timer Interface Module A
2-channel Timer Interface Module B
Enhanced Serial Communication Interface Module Computer Operating Properly Module
Serial Peripheral Interface Module Configuration Register Module
Periodic Wake-up Timebase Module
Arbiter Module
Prescaler Module
BEMF Module
PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO
PTD1/TACH1
PTD0/TACH0
PTE1/RXD
PTE0/TXD
PTE1/RXD PTE0/TXD
RXD TXD
PTD0/TACH0
PWM
PTA6/SS
SS
PTC0/MISO
MISO
PTC1/MOSI
MOSI
PTA5/SPSCK SPSCK
PTB0/AD0
ADOUT
LIN Physical Layer
Reset Control Autonomous Watchdog
SPI & CONTROL
Analog Multiplexer
Voltage Regulator
Switched VDD Driver &
Diagnostic
Wakeup Port
High Side Driver & Diagnostic
High Side Driver & Diagnostic
High Side Driver & Diagnostic
Half Bridge Driver &
Diagnostic
Half Bridge Driver &
Diagnostic
Half Bridge Driver &
Diagnostic
Half Bridge Driver &
Diagnostic
HALLPORT
Analog Port with Current
Source
Figure 2. 908E621 Simplified Internal Block Diagram
GND[1:4] VSUP[1:8]
TESTMODE LIN
RST_A IRQ_A
PTE1/RXD PTD0/TACH0
VSS VDD HVDD L0 HS1[a:b] HS2 HS3 HB1
HB2
HB3
HB4
H0 A0 A0CST
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View of Package
PTC4 /OSC1 PTC3 /OSC2
PTC2 / MCLK
PTB5 /AD5
PTB4 /AD4
PTB3 /AD3
IRQ
RST
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
RST_A
IRQ_A
LIN
.