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AT91CAP9S500A Dataheets PDF



Part Number AT91CAP9S500A
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description (AT91CAP9S250A / AT91CAP9S500A) Customizable Microcontroller Processor
Datasheet AT91CAP9S500A DatasheetAT91CAP9S500A Datasheet (PDF)

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Additional Embedded Memories – One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed.

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Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Additional Embedded Memories – One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed • External Bus Interface (EBI) – EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory, Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash™ • Metal Programmable (MP) Block – 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers) for AT91CAP9S500A/AT91CAP9S250A Respectively – Ten 512 x 36-bit Dual Port RAMs – Eight 512 x 72-bit Single Port RAMs – High Connectivity for Up to Three AHB Masters and Four AHB Slaves – Up to Seven AIC Interrupt Inputs – Up to Four DMA Hardware Handshake Interfaces – Delay Lines for Double Data Rate Interface – UTMI+ Full Connection – Up to 77 Dedicated I/Os • LCD Controller www.DataSheet4U.com – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider Screen Buffers • Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format • USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels • USB 2.0 High Speed (480 Mbits per second) Device Port – On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM – Integrated FIFOs and Dedicated DMA Channels – Integrated UTMI+ Physical Interface • Ethernet MAC 10/100 Base T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit • Multi-Layer Bus Matrix – Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus Bandwidth at Maximum 100 MHz System Clock Speed – Boot Mode Select Option, Remap Command • Fully-featured System Controller, Including – Reset Controller, Shutdown Controller Customizable Microcontroller Processor AT91CAP9S500A AT91CAP9S250A Summary Preliminary 6264AS–CAP–21-May-07 • • • • • • • • • • • • • • • – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-Time Timer Reset Controller (RSTC) – Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 8 to 16 MHz On-chip Oscillator – Two PLLs up to 240 MHz – One USB 480 MHz PLL Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-Time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOE) – 128 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output DMA Controller (DMAC) – Acts as one Bus Matrix Master – Embeds 4 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control – Supports Four External DMA Requests and Four Internal DMA Requests from the Metal Programmable Block (MPBlock) Twenty-two Peripheral DMA Controller Channels (PDC) One 2.0A and 2.0B Compliant CAN Controller – 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two Multimedia Card Interfaces (MCI) – SDCard/SDIO and MultiMedia™ Card 3.31 Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time .


AT91CAP9S250A AT91CAP9S500A AT91SC512384-128M


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