T431616D

tm TE CH T431616D/E SDRAM FEATURES Fast access time: 5/6/7 ns Fast clock rate: 200/166/143 MHz Self refresh mode: standard and low power Internal pipelined architecture 512K word x 16-bit x 2-bank Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function Individual byte controlled by LDQM and UDQM Auto Refresh and Self Refresh 4096 refresh cycles/64ms CKE power down mode JEDEC standard +3.3V±0.3V power supply Interface: LVTTL 50-pin 400 mil plastic TSOP II package 60-ball, 6.4x10.1mm VFBGA package Lead Free Package available for both TSOP II and VFBGA Low Operating Current for T431616E 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM GRNERAL DESCRIPTION The T431616D/E SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The T431616D/E provides for programmable Read or Write burst lengths of 1, 2, 4, 8, o...