Document
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ607
SWITCHING P-CHANNEL POWER MOS FET
DESCRIPTION
The 2SJ607 is P-channel MOS Field Effect Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER 2SJ607 2SJ607-S 2SJ607-ZJ 2SJ607-Z PACKAGE TO-220AB TO-262 TO-263 TO-220SMD
Note
FEATURES
• Super low on-state resistance: RDS(on)1 = 11 mΩ MAX. (VGS = −10 V, ID = −42 A) RDS(on)2 = 16 mΩ MAX. (VGS = −4.0 V, ID = −42 A) • Low input capacitance: Ciss = 7500 pF TYP. (VDS = −10 V, VGS = 0 V) • Built-in gate protection diode
Note TO-220SMD package is produced only in Japan
(TO-220AB)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
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VDSS VGSS ID(DC) ID(pulse) PT PT Tch Tstg
−60
V V A A W W °C °C A mJ (TO-262)
Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse)
Note1
m 20 m 83 m 332
160 1.5 150 −55 to +150 −50 250
Total Power Dissipation (TC = 25°C) Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy
Note2 Note2
IAS EAS
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1% 2. Starting Tch = 25°C, VDD = −30 V, RG = 25 Ω, VGS = −20 → 0 V (TO-263, TO-220SMD)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. D14655EJ3V0DS00 (3rd edition) Date Published July 2002 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
©
2000, 2001
2SJ607
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time
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TEST CONDITIONS VDS = −60 V, VGS = 0 V VGS =
MIN.
TYP.
MAX. −10
UNIT
µA µA
V S
m 20 V, VDS = 0 V
−1.5 45 −2.0 90 9.1 11 7500 1800 430 23 16 340 160
m 10
−2.5
VDS = −10 V, ID = −1 mA VDS = −10 V, ID = −42 A VGS = −10 V, ID = −42 A VGS = −4.0 V, ID = −42 A VDS = −10 V VGS = 0 V f = 1 MHz VDD = −30 V, ID = −42 A VGS = −10 V RG = 0 Ω
11 16
mΩ mΩ pF pF pF ns ns ns ns nC nC nC V ns nC
Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr
VDD= −48 V VGS = −10 V ID = −83 A IF = 83 A, VGS = 0 V IF = 83 A, VGS = 0 V di/dt = 100 A/ µs
188 30 48 1.0 64 150
Reverse Recovery Charge
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T. RG = 25 Ω PG. VGS = −20 → 0 V − ID VDD BVDSS VDS 50 Ω L VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T. RL PG. RG VDD VDS (−)
90% 90% 10% 10%
VGS (−) VGS
Wave Form
0
10%
VGS
.