CP80S56 Microcontroller Series Datasheet

CP80S56 Datasheet, PDF, Equivalent


Part Number

CP80S56

Description

(CP80S54 / CP80S56) EPROM/ROM-Based 8-Bit Microcontroller Series

Manufacture

ETC

Total Page 30 Pages
Datasheet
Download CP80S56 Datasheet


CP80S56
CP80S54/56
EPROM/ROM-Based 8-Bit Microcontroller Series
Devices Included in this Data Sheet:
CP80S54E/S56E : EPROM devices
CP80S54/S56 : Mask ROM devices
www.DataSheet4U.com
FEATURES
Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All ROM/EPROM area GOTO instruction
All ROM/EPROM area subroutine CALL instruction
8-bit wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O # EPROM/ROM (Byte) RAM (Byte)
CP80S54/S54E 18
16
512
49
CP80S56/S56E 18
16
1K
49
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Two I/O ports IOA and IOB with independent direction control (maximum 16 I/O pins)
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev0.1 Nov 30, 2005
P.1/CP 80S54/S56

CP80S56
CP80S54/56
GENERAL DESCRIPTION
The CP80S54/S56 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS
microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except
for program branches which take two cycles. The easy to use and easy to remember instruction set reduces
development time significantly.
The CP80S54/S56 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer
(PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O
pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,
Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are three oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.
The CP80S54/S54E address 512×13 of program memory, and the CP80S56/S56E address 1K×13 of program
memory.
The CP80S54/S56 can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
Oscillator
Circuit
Watchdog
Timer
ALU
Interrupt
Control
5-level
STACK
Program
Counter
EPROM
/ ROM
Timer0
FSR
SRAM
Instruction
Decoder
Accumulator
PORTA
PORTB
Rev0.1 Nov 30, 2005
P.2/CP80S54/S56


Features CP80S54/56 EPROM/ROM-Based 8-Bit Microco ntroller Series Devices Included in thi s Data Sheet: ‧ CP80S54E/S56E : EPROM devices ‧ CP80S54/S56 : Mask ROM dev ices FEATURES ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ Only 42 single word instruction s All instructions are single cycle exc ept for program branches which are two- cycle 13-bit wide instructions All ROM/ EPROM area GOTO instruction All ROM/EPR OM area subroutine CALL instruction 8-b it wide data path 5-level deep hardware stack Operating speed: DC-20 MHz clock input DC-100 ns instruction cycle Devi ce CP80S54/S54E CP80S56/S56E www.DataSh eet4U.com Pins # 18 18 I/O # 16 16 E PROM/ROM (Byte) 512 1K RAM (Byte) 49 4 9 ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ Direct, indir ect addressing modes for data accessing 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler Inte rnal Power-on Reset (POR) Built-in Low Voltage Detector (LVD) for Brown-out Re set (BOR) Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST) On chip Watchdog Timer (WDT) with intern.
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