IS42S16100A1 DYNAMIC RAM Datasheet

IS42S16100A1 Datasheet, PDF, Equivalent


Part Number

IS42S16100A1

Description

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

Manufacture

ISSI

Total Page 30 Pages
Datasheet
Download IS42S16100A1 Datasheet


IS42S16100A1
IS42S16100A1
ISSI®
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
August 2003
FEATURES
• Clock frequency: 166, 143, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
www.DataSheet4U.com Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
• Lead-free package option
PIN DESCRIPTIONS
A0-A11
A0-A10
A11
A0-A7
DQ0 to DQ15
CLK
CKE
CS
RAS
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data DQ
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100A1 is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 GND
49 DQ15
48 IDQ14
47 GNDQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 GNDQ
40 DQ9
39 DQ8
38 VDDQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 GND
CAS
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
08/12/03
1

IS42S16100A1
IS42S16100A1
ISSI ®
PIN FUNCTIONS
Pin No.
20 to 24
27 to 32
Symbol
A0-A10
Type
Input Pin
19 A11 Input Pin
16 CAS Input Pin
34 CKE Input Pin
35 CLK Input Pin
18 CS Input Pin
2, 3, 5, 6, 8, 9, 11 DQ0 to
12, 39, 40, 42, 43, DQ15
45, 46, 48, 49
14, 36
LDQM,
UDQM
DQ Pin
Input Pin
17 RAS Input Pin
15 WE Input Pin
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
VDDQ
VDD
GNDQ
GND
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts
automatically after the burst access.
These signals become part of the OP CODE during mode register set command
input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
CAS, in conjunction with the RAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device. When
is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,
invalid. When CKE is LOW, the device will be in either the power-down mode, the
clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function
corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the
“Command Truth Table” item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
08/12/03


Features IS42S16100A1 512K Words x 16 Bits x 2 Ba nks (16-MBIT) SYNCHRONOUS DYNAMIC RAM F EATURES • Clock frequency: 166, 143, 100 MHz • Fully synchronous; all sign als referenced to a positive clock edge • Two banks can be operated simultan eously and independently • Dual inter nal bank controlled by A11 (bank select ) • Single 3.3V power supply • LVTT L interface • Programmable burst leng th – (1, 2, 4, 8, full page) • Prog rammable burst sequence: Sequential/Int erleave • Auto refresh, self refresh • 4096 refresh cycles every 64 ms Ran dom column address every clock cycle ww w.DataSheet4U.com • • Programmable CAS latency (2, 3 clocks) • Burst rea d/write and burst read/single write ope rations capability • Burst terminatio n by burst stop and precharge command Byte controlled by LDQM and UDQM • Package 400-mil 50-pin TSOP II • Lea d-free package option ISSI August 2003 ® DESCRIPTION ISSI’s 16Mb Synchro nous DRAM IS42S16100A1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The .
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