Document
IS42S16100C1
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
SEPTEMBER 2009
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Two banks can be operated simultaneously and independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Industrial temperature up to 143 MHz
• Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
• Lead-free package option
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is
organized as a 524.