IS42S16100C1 DYNAMIC RAM Datasheet

IS42S16100C1 Datasheet, PDF, Equivalent


Part Number

IS42S16100C1

Description

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

Manufacture

ISSI

Total Page 30 Pages
Datasheet
Download IS42S16100C1 Datasheet


IS42S16100C1
IS42S16100C1
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
SEPTEMBER 2009
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Industrial temperature up to 143 MHz
• Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
• Lead-free package option
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 GND
49 DQ15
48 IDQ14
47 GNDQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 GNDQ
40 DQ9
39 DQ8
38 VDDQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 GND
PIN DESCRIPTIONS
A0-A11 Address Input
A0-A10 Row Address Input
A11 Bank Select Address
A0-A7 Column Address Input
DQ0 to DQ15 Data DQ
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
LDQM Lower Bye, Input/Output Mask
UDQM Upper Bye, Input/Output Mask
VDD Power
GND Ground
VDDQ Power Supply for DQ Pin
GNDQ Ground for DQ Pin
NC No Connection
Copyright © 2007 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
08/24/09
1

IS42S16100C1
IS42S16100C1
PIN CONFIGURATION
package code: B 60 bALL fbga (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1234567
A
VSS DQ15
B
DQ14 VSSQ
C
DQ13 VDDQ
D
DQ12 DQ11
E
DQ10 VSSQ
F
DQ9 VDDQ
G
DQ8 NC
H
NC NC
J
NC UDQM
K
NC CLK
L
CKE NC
M
A11 A9
N
A8 A7
P
A6 A5
R
VSS A4
PIN DESCRIPTIONS
A0-A10 Row Address Input
A0-A7 Column Address Input
A11 Bank Select Address
DQ0 to DQ15 Data I/O
CLK System Clock Input
CKE Clock Enable
CS
RAS
CAS
Chip Select
Row Address Strobe Command
Column Address Strobe Command
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
VDDQ DQ5
VSSQ DQ6
NC DQ7
VDD NC
LDQM WE
RAS CAS
NC CS
NC NC
A0 A10
A2 A1
A3 VDD
WE Write Enable
LDQM, UDQM x16 Input/Output Mask
Vdd Power
Vss Ground
Vddq Power Supply for I/O Pin
Vssq Ground for I/O Pin
NC No Connection
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  F
08/24/09


Features IS42S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM SEPTEMBER 2009 FEATURES • Clock f requency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks ca n be operated simultaneously and indepe ndently • Dual internal bank control led by A11 (bank select) • Single 3. 3V power supply • LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) • Programmable bur st sequence: Sequential/Interleave • 4096 refresh cycles every 64 ms • R andom column address every clock cycle • Programmable CAS latency (2, 3 clo cks) • Burst read/write and burst re ad/single write operations capability Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Industrial tempe rature up to 143 MHz • Packages 400- mil 50-pin TSOP-II, 60-ball fBGA • L ead-free package option DESCRIPTION IS SI’s 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524.
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