IS61LV25616 STATIC RAM Datasheet

IS61LV25616 Datasheet, PDF, Equivalent


Part Number

IS61LV25616

Description

256 X 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

Manufacture

Integrated Circuit Solution

Total Page 10 Pages
Datasheet
Download IS61LV25616 Datasheet


IS61LV25616
IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10, 12, and 15 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
FUNCTIONALwww.DataSheet4U.com BLOCK DIAGRAM
DESCRIPTION
The 1+51 IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using 1+51's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power consump-
tion devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TF-
BGA.
A0-A17
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE CONTROL
WE CIRCUIT
UB
LB
256K x 16
MEMORY ARRAY
COLUMN I/O
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR040-0C
1

IS61LV25616
IS61LV25616
PIN CONFIGURATIONS
44-Pin TSOP-2 and SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
48-Pin TF-BGA
44 A17
43 A16
42 A15
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 Vcc
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A14
26 A13
25 A12
24 A11
23 A10
1 23 45 6
A LB OE A0 A1 A2 N/C
B I/O0 UB A3 A4 CE I/O8
C I/O1 I/O2 A5
A6 I/O10 I/O9
D GND I/O3 A17 A7 I/O11 Vcc
E Vcc I/O4 NC A16 I/O12 GND
F I/O6 I/O5 A14 A15 I/O13 I/O14
G I/O7 NC A12 A13 WE I/O15
H
NC A8
A9 A10 A11 NC
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
OE Output Enable Input
WE Write Enable Input
TRUTH TABLE
LB
UB
NC
Vcc
GND
Mode
WE CE OE LB UB
Not Selected
XHXXX
Output Disabled
H
L
H
X
X
X L XHH
Read
HL L LH
HL LHL
HL L L L
Write
L LXLH
L LXHL
LLXLL
2
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
I/O PIN
I/O0-I/O7 I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
ISB, ISB
ICC
ICC
ICC
Integrated Circuit Solution Inc.
SR040-0C


Features IS61LV25616 FEATURES • • • • • 256 K x 16 HIGH SPEED ASYNCHRONOUS CMOS STA TIC RAM WITH 3.3V SUPPLY High-speed acc ess time: 8, 10, 12, and 15 ns CMOS low power operation TTL compatible interfa ce levels Single 3.3V ± 10% power supp ly Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower by tes • Industrial temperature available DESCRIPTION The 1+51 IS61LV25616 is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using 1+51's high-perf ormance CMOS technology. This highly re liable process coupled with innovative circuit design techniques, yields high- performance and low power consumption d evices. When CE is HIGH (deselected), t he device assumes a standby mode at whi ch the power dissipation can be reduced down with CMOS input levels. Easy memo ry expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading .
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