b2 SRAM. K7I163682B Datasheet


K7I163682B SRAM. Datasheet pdf. Equivalent


K7I163682B


(K7I163682B / K7I161882B) 1Mx18-bit DDRII CIO b2 SRAM
K7I163682B K7I161882B
Document Title

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Add the speed bin (-33, -30) 2. Delete the speed bin (-25, -13) 1. Change the Boundary scan exit order. 2. Correct the Overshoot and Undershoot timing diagram. 1. Add the speed bin (-25) 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Add the power up/down sequencing comment. 2. Update the DC current parameter (Icc and Isb). 3. Change the Max. speed bin from -33 to -30. 1. Change the ISB1. Speed Bin -30 -25 -20 -16 1.0 2.0 1. Final spec release 1. Delete the x8 Org. 2. Delete the 300MHz speed bin 1. Add the 300MHz speed bin 1. Change the stand-by current(ISB1) before after Isb1 -30 : 230 260 -25 : 210 240 -20 : 190 220 -16 : 170 200 From 200 180 160 140 To 230 210 190 170 Oct. 31, 2003 Nov. 28, 2003 Final Final Draft Date Oct. 23. 2002 Oct. 24. 2002 Remark Advance Premilinary

0.2

Dec. 16, 2002

Premilinary

0.3 0.4

Jan. 27, 2003 Mar. 20, 2003

Premilinary Premilinary

0.5

April. 4, 2003

Premilinary

0.6

June. 20, 2003

Premilinary

0.7
www.DataSheet4U.com

Oct. 20. 2003

Premilinary

3.0 3.1

June. 18, 2004 July. 28, 2004

Final Final

The attached data...



K7I163682B
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
Document Title
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Add the speed bin (-33, -30)
2. Delete the speed bin (-25, -13)
0.2 1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.
0.3 1. Add the speed bin (-25)
0.4 1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
0.5 1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
0.6 1. Add the power up/down sequencing comment.
2. Update the DC current parameter (Icc and Isb).
3. Change the Max. speed bin from -33 to -30.
www.DataSheet4U.com
0.7 1. Change the ISB1.
Speed Bin
-30
-25
-20
-16
From
200
180
160
140
To
230
210
190
170
1.0 1. Final spec release
2.0 1. Delete the x8 Org.
2. Delete the 300MHz speed bin
3.0 1. Add the 300MHz speed bin
3.1 1. Change the stand-by current(ISB1)
before after
Isb1 -30 : 230
260
-25 : 210
240
-20 : 190
220
-16 : 170
200
Draft Date
Oct. 23. 2002
Oct. 24. 2002
Dec. 16, 2002
Jan. 27, 2003
Mar. 20, 2003
April. 4, 2003
June. 20, 2003
Oct. 20. 2003
Oct. 31, 2003
Nov. 28, 2003
June. 18, 2004
July. 28, 2004
Remark
Advance
Premilinary
Premilinary
Premilinary
Premilinary
Premilinary
Premilinary
Premilinary
Final
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - July. 2004
Rev 3.1

K7I163682B
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus .
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 13x15mm
Organization
Part
Number
Cycle
Time
Access
Time
Unit
K7I163682B-FC30 3.3
0.45 ns
X36
K7I163682B-FC25 4.0
0.45 ns
K7I163682B-FC20 5.0
0.45 ns
K7I163682B-FC16 6.0
0.50 ns
K7I161882B-FC30 3.3
0.45 ns
X18
K7I161882B-FC25 4.0
0.45 ns
K7I161882B-FC20 5.0
0.45 ns
K7I161882B-FC16 6.0
0.50 ns
FUNCTIONAL BLOCK DIAGRAM
DATA
REG
ADDRESS
A0
18 (or
19)
ADD REG
&
BURST
LOGIC
18
(or 19)
LD
R/W
BWX
CTRL
4(or 2) LOGIC
36 (or 18)
36 (or 18)
WRITE DRIVER
512Kx36
(1Mx18)
MEMORY
ARRAY
36
(or 18)
K
K CLK
C GEN
C SELECT OUTPUT CONTROL
72
(or 36)
36 (or 18)
DQ
CQ, CQ
(Echo Clock out)
Notes: 1. Numbers in ( ) are for x18 device.
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
- 2 - July. 2004
Rev 3.1




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