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Signal Controllers. 56853 Datasheet

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Signal Controllers. 56853 Datasheet






56853 Controllers. Datasheet pdf. Equivalent




56853 Controllers. Datasheet pdf. Equivalent





Part

56853

Description

16-bit Digital Signal Controllers



Feature


56853 Data Sheet Technical Data www.Dat aSheet4U.com 56800E 16-bit Digital Sig nal Controllers DSP56853 Rev. 6 01/200 7 freescale.com 56853 General Descrip tion • 120 MIPS at 120MHz • 12K x 1 6-bit Program SRAM • 4K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Acce ss up to 2M words of program memory or 8M of data memory • Chip Select Logic for glue-less interface to RO.
Manufacture

Freescale Semiconductor

Datasheet
Download 56853 Datasheet


Freescale Semiconductor 56853

56853; M and SRAM • Six (6) independent chann els of DMA • Enhanced Synchronous Ser ial Interfaces (ESSI) • Two (2) Seria l Communication Interfaces (SCI) • Se rial Port Interface (SPI) • 8-bit Par allel Host Interface • General Purpos e 16-bit Quad Timer • JTAG/Enhanced O n-Chip Emulation (OnCE™) for unobtrus ive, real-time debugging • Computer O perating Properly (COP)/Watchdog Tim.


Freescale Semiconductor 56853

er • Time-of-Day (TOD) • 128 LQFP pa ckage • Up to 41 GPIO VDDIO 6 11 VD D 6 VSSIO 10 VSS VDDA 6 VSSA JTAG/ Enhanced OnCE Program Controller and Ha rdware Looping Unit Address Generation Unit 16-Bit 56800E Core Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Inp ut Registers Four 36-bit Accumulators B it Manipulation Unit PAB PDB CDBR CDBW Memory Program Memory 12.


Freescale Semiconductor 56853

,288 x 16 SRAM Boot ROM 1024 x 16 ROM Da ta Memory 4,096 x 16 SRAM XDB2 XAB1 XA B2 PAB PDB CDBR CDBW IPBus Bridge (IPB B) IPWDB Decoding Peripherals A0-20 [2 0:0] D0-D15 [15:0] RD Enable WR Enable CS0-CS3[3:0] or GPIOA0-A3[3:0] Bus Cont rol External Address Bus Switch Externa l Data Bus Switch External Bus Interfac e Unit ESSI0 or GPIOC IPRDB IPAB DMA Requests Core CL.

Part

56853

Description

16-bit Digital Signal Controllers



Feature


56853 Data Sheet Technical Data www.Dat aSheet4U.com 56800E 16-bit Digital Sig nal Controllers DSP56853 Rev. 6 01/200 7 freescale.com 56853 General Descrip tion • 120 MIPS at 120MHz • 12K x 1 6-bit Program SRAM • 4K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Acce ss up to 2M words of program memory or 8M of data memory • Chip Select Logic for glue-less interface to RO.
Manufacture

Freescale Semiconductor

Datasheet
Download 56853 Datasheet




 56853
56853
Data Sheet
Technical Data
56800E
16-bit Digital Signal Controllers
www.DataSheet4U.com
DSP56853
Rev. 6
01/2007
freescale.com




 56853




 56853
56853 General Description
• 120 MIPS at 120MHz
• 12K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program memory or 8M of
data memory
• Chip Select Logic for glue-less interface to ROM and
SRAM
• Six (6) independent channels of DMA
• Enhanced Synchronous Serial Interfaces (ESSI)
• Two (2) Serial Communication Interfaces (SCI)
• Serial Port Interface (SPI)
• 8-bit Parallel Host Interface
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of-Day (TOD)
• 128 LQFP package
• Up to 41 GPIO
6
JTAG/
Enhanced
OnCE
VDDIO
11
VDD
6
VSSIO
10
VSS VDDA
6
VSSA
16-Bit
56800E Core
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
12,288 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4,096 x 16 SRAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System Bus
Control
DMA
6 channel
IPBus Bridge (IPBB)
Decoding
Peripherals
A0-20 [20:0]
D0-D15 [15:0]
RD Enable
WR Enable
CS0-CS3[3:0] or
GPIOA0-A3[3:0]
External Address
Bus Switch
External Data
Bus Switch
Bus Control
External Bus
Interface Unit
2 SCI
or
GPIOE
ESSI0
or
GPIOC
46
Quad
Timer
or
GPIOG
SPI
or
GPIOF
Host Interrupt
Interface Controller
or
GPIOB
4 4 16 IRQA
IRQB
56853 Block Diagram
COP/
Watch-
dog
POR
CLKO
IPBus CLK
System
3 MODEA-C or
(GPIOH0-H2)
COP/TOD CLK Integration
Module
RSTO
RESET
Time
of
Day
Clock
Generator
OSC PLL
EXTAL
XTAL
Freescale Semiconductor
56853 Technical Data, Rev. 6
3






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