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Signal Controllers. 56858 Datasheet

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Signal Controllers. 56858 Datasheet






56858 Controllers. Datasheet pdf. Equivalent




56858 Controllers. Datasheet pdf. Equivalent





Part

56858

Description

16-bit Digital Signal Controllers



Feature


56858 Data Sheet Technical Data www.Dat aSheet4U.com 56800E 16-bit Digital Sig nal Controllers DSP56858 Rev. 6 01/200 7 freescale.com DSP56858 General Desc ription • 120 MIPS at 120MHz • 40K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or 8M data memory • Chip Select Logi c for glue-less interface to R.
Manufacture

Freescale Semiconductor

Datasheet
Download 56858 Datasheet


Freescale Semiconductor 56858

56858; OM and SRAM • Six (6) independent chan nels of DMA • Two (2) Enhanced Synchr onous Serial Interfaces (ESSI) • Two (2) Serial Communication Interfaces (SC I) • Serial Port Interface (SPI) • 8-bit Parallel Host Interface • Gener al Purpose 16-bit Quad Timer • JTAG/E nhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • C omputer Operating Properly (COP)/Wat.


Freescale Semiconductor 56858

chdog Timer • Time-of -Day (TOD) • 1 44 LQFP and 144 MAPBGA packages • Up to 47 GPIO 6 VDDIO 12 VDD 8 VSSIO 1 4 VSS VDDA 8 VSSA 2 JTAG/ Enhanced O nCE Program Controller and Hardware Loo ping Unit Address Generation Unit 16-B it 56800E Core Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registe rs Four 36-bit Accumulators Bit Manipul ation Unit PAB PDB CDBR C.


Freescale Semiconductor 56858

DBW Memory Program Memory 40,960 x 16 S RAM Boot ROM 1024 x 16 ROM Data Memory 24,576 x 16 SRAM XDB2 XAB1 XAB2 PAB PD B CDBR CDBW System Bus Control DMA 6 channel Core CLK IPBus Bridge (IPBB) I PWDB Decoding Peripherals A0-20 [20:0] D0-D15 [15:0] RD Enable WR Enable CS0- CS3[3:0] or GPIOA0-A3 Bus Control Exter nal Address Bus Switch External Data Bu s Switch External .

Part

56858

Description

16-bit Digital Signal Controllers



Feature


56858 Data Sheet Technical Data www.Dat aSheet4U.com 56800E 16-bit Digital Sig nal Controllers DSP56858 Rev. 6 01/200 7 freescale.com DSP56858 General Desc ription • 120 MIPS at 120MHz • 40K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or 8M data memory • Chip Select Logi c for glue-less interface to R.
Manufacture

Freescale Semiconductor

Datasheet
Download 56858 Datasheet




 56858
56858
Data Sheet
Technical Data
56800E
16-bit Digital Signal Controllers
www.DataSheet4U.com
DSP56858
Rev. 6
01/2007
freescale.com




 56858




 56858
DSP56858 General Description
• 120 MIPS at 120MHz
• 40K x 16-bit Program SRAM
• 24K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program memory or 8M data
memory
• Chip Select Logic for glue-less interface to ROM and
SRAM
• Six (6) independent channels of DMA
• Two (2) Enhanced Synchronous Serial Interfaces
(ESSI)
• Two (2) Serial Communication Interfaces (SCI)
• Serial Port Interface (SPI)
• 8-bit Parallel Host Interface
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of -Day (TOD)
• 144 LQFP and 144 MAPBGA packages
• Up to 47 GPIO
6
JTAG/
Enhanced
OnCE
VDDIO
12
VDD
8
VSSIO
14
VSS VDDA
8
VSSA
2
16-Bit
56800E Core
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
40,960 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System Bus
Control
DMA
6 channel
IPBus Bridge (IPBB)
Decoding
Peripherals
A0-20 [20:0]
D0-D15 [15:0]
RD Enable
WR Enable
CS0-CS3[3:0] or
GPIOA0-A3
External Address
Bus Switch
External Data External Bus
Bus Switch Interface Unit
Bus Control
2 SCI ESSI0
or or
GPIOE GPIOC
ESSI1
or
GPIOD
Quad
Timer
or
GPIOG
SPI
or
GPIOF
Host Interrupt
Interface Controller
or
GPIOB
4 6 6 4 4 16 IRQA
IRQB
56858 Block Diagram
COP/
Watch-
dog
IPBus CLK
POR
System
CLKO
3
MODE A-C or
GPIOH0-H2
COP/TOD CLK Integration
Module
RSTO
RESET
Time
of
Day
Clock
Generator
OSC PLL
EXTAL
XTAL
Freescale Semiconductor
56858 Technical Data, Rev. 6
3



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